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openmsp430 WebSVN RSS feed - openmsp430 http://opencores.com/websvn,listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F& Mon, 20 May 2013 13:31:38 +0100 FeedCreator 1.7.2 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=186 <div>Rev 186 - olivier.girard (7 file(s) modified)</div><div>Fixed Hardware Multiplier byte operations bug: <a href="http://opencores.org/bug,assign,2247" target="_blank">http://opencores.org/bug,assign,2247</a></div>~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v olivier.girard Mon, 08 Apr 2013 20:00:10 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=186 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=180 <div>Rev 180 - olivier.girard (29 file(s) modified)</div><div>Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v olivier.girard Mon, 25 Feb 2013 21:23:18 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=180 Update all linker scripts with a simplified version. Thanks to Mihai ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=178 <div>Rev 178 - olivier.girard (11 file(s) modified)</div><div>Update all linker scripts with a simplified version. Thanks to Mihai ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0 ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1 ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/linker.x ~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/software/leds/linker.x olivier.girard Sat, 16 Feb 2013 21:39:23 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=178 Update hardware breakpoint unit with the followings: - fixed hardware breakpoint ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=175 <div>Rev 175 - olivier.girard (14 file(s) modified)</div><div>Update hardware breakpoint unit with the followings: - fixed hardware breakpoint ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v ~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl olivier.girard Wed, 30 Jan 2013 21:21:42 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=175 The serial debug interface now supports the I2C protocol (in ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=154 <div>Rev 154 - olivier.girard (82 file(s) modified)</div><div>The serial debug interface now supports the I2C protocol (in ...</div>+ /openmsp430/trunk/core/bench/verilog/dbg_i2c_tasks.v ~ /openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v + /openmsp430/trunk/core/bench/verilog/io_cell.v ~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v + /openmsp430/trunk/core/rtl/verilog/omsp_dbg_i2c.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm ~ /openmsp430/trunk/core/sim/rtl_sim/run ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all ~ /openmsp430/trunk/core/sim/rtl_sim/src/core.f - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.v - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43 - /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.prj olivier.girard Mon, 15 Oct 2012 20:44:20 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=154 Add possibility to configure custom Program, Data and Peripheral memory ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=151 <div>Rev 151 - olivier.girard (22 file(s) modified)</div><div>Add possibility to configure custom Program, Data and Peripheral memory ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c + /openmsp430/trunk/core/sim/rtl_sim/bin/omsp_config.sh ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43 ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim + /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/omsp_config.sh ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim + /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/omsp_config.sh ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim + /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/omsp_config.sh olivier.girard Sun, 22 Jul 2012 22:24:11 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=151 Update simulation regression result parser. Fixed failing SFR test (due to ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=149 <div>Rev 149 - olivier.girard (7 file(s) modified)</div><div>Update simulation regression result parser. Fixed failing SFR test (due to ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v + /openmsp430/trunk/core/sim/rtl_sim/bin/parse_results ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all ~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43 ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v olivier.girard Thu, 19 Jul 2012 20:21:12 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=149 Add Dhrystone and CoreMark benchmarks to the simulation environment. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=145 <div>Rev 145 - olivier.girard (80 file(s) modified)</div><div>Add Dhrystone and CoreMark benchmarks to the simulation environment.</div>~ /openmsp430/trunk/core/bench/verilog/registers.v ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0 + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark.md5 + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_list_join.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_main.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_matrix.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_state.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_util.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/Coremark-requirements.doc + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/LICENSE.DOC + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/r01an0757eu_rx.pdf + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/LICENSE.txt + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/Makefile + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430 + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.mak + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/readme.txt + /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/release_notes.txt + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry21a.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry21b.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/makefile + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry21a.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry21b.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/Dhrystone.pnproj + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhyrstone.pro + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/estubs.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/Makefile + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/ReadMe.txt + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/timers_b.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/z8obj + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1 + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_1.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_2.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/doc + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/doc/reu05b0134_rxap.pdf + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/makefile + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/bymanuf + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/byperf + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/cc_dry2 + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/cc_dry2reg + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/clarify.doc + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry-2.1.p + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry.h + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry.p + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_1.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_2.c + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_c.dif + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/doit + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/Makefile + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/pure2_1.dif + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/RATIONALE + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/README + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/README.RER + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/results + /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/submit.frm ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/sandbox.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x olivier.girard Wed, 30 May 2012 21:03:05 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=145 Beautify the linker script examples. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=142 <div>Rev 142 - olivier.girard (2 file(s) modified)</div><div>Beautify the linker script examples.</div>~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x olivier.girard Wed, 09 May 2012 20:19:02 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=142 Update verification environment to support MSPGCC Uniarch (based on GCC ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=141 <div>Rev 141 - olivier.girard (68 file(s) modified)</div><div>Update verification environment to support MSPGCC Uniarch (based on GCC ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c + /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/main.c ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile + /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/omsp_system.h - /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/periph.x ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sandbox.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.s43 olivier.girard Sat, 05 May 2012 21:22:06 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=141 Update simulation scripts to support Cygwin out of the box ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=138 <div>Rev 138 - olivier.girard (13 file(s) modified)</div><div>Update simulation scripts to support Cygwin out of the box ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c ~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/rtlsim.sh ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/run/run ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/rtlsim.sh ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/run olivier.girard Mon, 23 Apr 2012 11:10:00 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=138 Add full ASIC support (low-power modes, DFT, ...). Improved serial debug ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=134 <div>Rev 134 - olivier.girard (116 file(s) modified)</div><div>Add full ASIC support (low-power modes, DFT, ...). Improved serial debug ...</div>~ /openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v ~ /openmsp430/trunk/core/bench/verilog/msp_debug.v ~ /openmsp430/trunk/core/bench/verilog/registers.v ~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v + /openmsp430/trunk/core/rtl/verilog/omsp_and_gate.v + /openmsp430/trunk/core/rtl/verilog/omsp_clock_gate.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v + /openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v + /openmsp430/trunk/core/rtl/verilog/omsp_scan_mux.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v + /openmsp430/trunk/core/rtl/verilog/omsp_sync_reset.v + /openmsp430/trunk/core/rtl/verilog/omsp_wakeup_cell.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh ~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude.dat ~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude_bits.dat ~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_iccr_merge.cf ~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.ccf ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh - /openmsp430/trunk/core/sim/rtl_sim/bin/template.def + /openmsp430/trunk/core/sim/rtl_sim/bin/template.x ~ /openmsp430/trunk/core/sim/rtl_sim/run/load_waveform.sav ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_coverage_analysis - /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def + /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/main.c ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile + /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/periph.x ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v + /openmsp430/trunk/core/sim/rtl_sim/src/core.f + /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v + /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/nmi.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v + /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/scan.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/scan.v + /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/sfr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f + /openmsp430/trunk/core/sim/rtl_sim/src/submit.prj ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v + /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.v + /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v + /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v ~ /openmsp430/trunk/core/synthesis/altera/design_files.v ~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl ~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl + /openmsp430/trunk/core/synthesis/synopsys/run_tmax ~ /openmsp430/trunk/core/synthesis/synopsys/synthesis.tcl + /openmsp430/trunk/core/synthesis/synopsys/tmax.tcl ~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj olivier.girard Thu, 22 Mar 2012 20:31:06 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=134 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=128 <div>Rev 128 - olivier.girard (8 file(s) modified)</div><div>Fixed CALL x(SR) bug (see Bugtracker <a href="http://opencores.org/bug,view,2111" target="_blank">http://opencores.org/bug,view,2111</a> )</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/template.def ~ /openmsp430/trunk/core/sim/rtl_sim/run ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v olivier.girard Fri, 16 Dec 2011 21:05:46 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=128 Add coverage report generation (NCVERILOG only) Add support for the ISIM ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=122 <div>Rev 122 - olivier.girard (11 file(s) modified)</div><div>Add coverage report generation (NCVERILOG only) Add support for the ISIM ...</div>+ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude.dat + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude_bits.dat + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_iccr_merge.cf + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.ccf + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.tcl ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c ~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all + /openmsp430/trunk/core/sim/rtl_sim/run/run_coverage_analysis olivier.girard Wed, 05 Oct 2011 20:29:45 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=122 Add linker script example. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=115 <div>Rev 115 - olivier.girard (1 file(s) modified)</div><div>Add linker script example.</div>+ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x olivier.girard Sun, 29 May 2011 19:41:21 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=115 Re-organized the "openMSP430_defines.v" file. ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=111 <div>Rev 111 - olivier.girard (185 file(s) modified)</div><div>Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug ...</div>~ /openmsp430/trunk/core/bench/verilog/msp_debug.v ~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v + /openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/template.def ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all + /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43 ~ /openmsp430/trunk/core/synthesis/actel/design_files.v ~ /openmsp430/trunk/core/synthesis/altera/design_files.v ~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl ~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl ~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/registers.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v + /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v ~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v ~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v ~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v + /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v + /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj olivier.girard Fri, 20 May 2011 20:39:02 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=111 Separated the Timer A defines from the openMSP430 ones. Added the ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=106 <div>Rev 106 - olivier.girard (35 file(s) modified)</div><div>Separated the Timer A defines from the openMSP430 ones. Added the ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v + /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_defines.v + /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile olivier.girard Fri, 25 Mar 2011 22:01:03 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=106 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=105 <div>Rev 105 - olivier.girard (20 file(s) modified)</div><div>Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f olivier.girard Thu, 10 Mar 2011 21:10:30 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=105 Removed the timescale from all RTL files. Added possibility to exclude ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=103 <div>Rev 103 - olivier.girard (24 file(s) modified)</div><div>Removed the timescale from all RTL files. Added possibility to exclude ...</div>~ /openmsp430/trunk/core/bench/verilog/msp_debug.v ~ /openmsp430/trunk/core/bench/verilog/ram.v ~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v + /openmsp430/trunk/core/bench/verilog/timescale.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v - /openmsp430/trunk/core/rtl/verilog/timescale.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f olivier.girard Sat, 05 Mar 2011 14:44:48 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=103 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=102 <div>Rev 102 - olivier.girard (3 file(s) modified)</div><div>Fixed bug reported by Mihai ( <a href="http://opencores.org/bug,view,1955" target="_blank">http://opencores.org/bug,view,1955</a> ). The following PUSH ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v olivier.girard Fri, 04 Mar 2011 22:02:09 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=102

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