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openmsp430 WebSVN RSS feed - openmsp430 http://opencores.com/websvn,listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F& Mon, 20 May 2013 19:20:14 +0100 FeedCreator 1.7.2 update changelog... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=125 <div>Rev 125 - olivier.girard (1 file(s) modified)</div><div>update changelog...</div>~ /openmsp430/trunk/ChangeLog_tools.txt olivier.girard Thu, 27 Oct 2011 18:36:03 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=125 Improved gdbproxy robustness. Create a workaround to prevent GDB from freezing ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=124 <div>Rev 124 - olivier.girard (4 file(s) modified)</div><div>Improved gdbproxy robustness. Create a workaround to prevent GDB from freezing ...</div>~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl ~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_uart.tcl ~ /openmsp430/trunk/tools/openmsp430-gdbproxy/commands.tcl ~ /openmsp430/trunk/tools/openmsp430-gdbproxy/server.tcl olivier.girard Thu, 27 Oct 2011 07:38:36 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=124 update changelog... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=123 <div>Rev 123 - olivier.girard (1 file(s) modified)</div><div>update changelog...</div>~ /openmsp430/trunk/ChangeLog_core.txt olivier.girard Wed, 05 Oct 2011 20:31:42 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=123 Add coverage report generation (NCVERILOG only) Add support for the ISIM ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=122 <div>Rev 122 - olivier.girard (11 file(s) modified)</div><div>Add coverage report generation (NCVERILOG only) Add support for the ISIM ...</div>+ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude.dat + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude_bits.dat + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_iccr_merge.cf + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.ccf + /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.tcl ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c ~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all + /openmsp430/trunk/core/sim/rtl_sim/run/run_coverage_analysis olivier.girard Wed, 05 Oct 2011 20:29:45 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=122 Add a new FPGA example for the LX9 Microboard from ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=121 <div>Rev 121 - olivier.girard (97 file(s) modified)</div><div>Add a new FPGA example for the LX9 Microboard from ...</div>+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/msp430f1121a.pdf + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/hardware.h + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/main.c + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/Makefile + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/hardware.h + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/main.c + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/Makefile + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/README.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.h + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.s + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/ta_uart.lst + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/openmsp430.xise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.bit + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.ucf + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_v6_2_readme.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.asy + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.gise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.ngc + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.veo + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xco + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_flist.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_readme.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_xmdf.tcl + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.asy + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.cdc + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ejp + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.gise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ngc + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.veo + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xco + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_flist.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_readme.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_xmdf.tcl + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgc + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgp + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.log + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.asy + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.gise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.ngc + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.veo + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xco + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_flist.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_xmdf.tcl + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.asy + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.gise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.ngc + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.veo + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xco + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xise + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_flist.txt + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_xmdf.tcl + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/summary.log + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/io_mux.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430 + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_alu.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_clock_module.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_uart.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_execution_unit.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_frontend.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_mem_backbone.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_multiplier.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_register_file.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sfr.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sync_cell.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_watchdog.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_defines.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_undefines.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_gpio.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_8b.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_16b.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openMSP430_fpga.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/README olivier.girard Mon, 25 Jul 2011 20:11:04 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=121 update tools changelog... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=120 <div>Rev 120 - olivier.girard (1 file(s) modified)</div><div>update tools changelog...</div>~ /openmsp430/trunk/ChangeLog_tools.txt olivier.girard Fri, 24 Jun 2011 13:22:03 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=120 Slight improvement of the gdbproxy to improve the support of ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=119 <div>Rev 119 - olivier.girard (1 file(s) modified)</div><div>Slight improvement of the gdbproxy to improve the support of ...</div>~ /openmsp430/trunk/tools/openmsp430-gdbproxy/commands.tcl olivier.girard Fri, 24 Jun 2011 12:35:53 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=119 Changelog update (move to modified BSD license). http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=118 <div>Rev 118 - olivier.girard (1 file(s) modified)</div><div>Changelog update (move to modified BSD license).</div>~ /openmsp430/trunk/ChangeLog_core.txt olivier.girard Thu, 23 Jun 2011 19:33:04 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=118 To facilitate commercial adoption of the openMSP430, the core has ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=117 <div>Rev 117 - olivier.girard (22 file(s) modified)</div><div>To facilitate commercial adoption of the openMSP430, the core has ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_defines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v olivier.girard Thu, 23 Jun 2011 19:30:51 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=117 Update documentation to reflect the latest core updates. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=116 <div>Rev 116 - olivier.girard (21 file(s) modified)</div><div>Update documentation to reflect the latest core updates.</div>~ /openmsp430/trunk/ChangeLog_core.txt ~ /openmsp430/trunk/ChangeLog_tools.txt ~ /openmsp430/trunk/doc/html/area_speed.html ~ /openmsp430/trunk/doc/html/core.html ~ /openmsp430/trunk/doc/html/files_directory_description.html ~ /openmsp430/trunk/doc/html/images/core_integration.odg ~ /openmsp430/trunk/doc/html/images/core_integration.png + /openmsp430/trunk/doc/html/images/cpu_mem_space.odg + /openmsp430/trunk/doc/html/images/cpu_mem_space.png + /openmsp430/trunk/doc/html/images/openmsp430-extra_info.png ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy-ddd.png ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy-eclipse.png ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy.png ~ /openmsp430/trunk/doc/html/images/openmsp430-loader_lin.png ~ /openmsp430/trunk/doc/html/images/openmsp430-minidebug.png ~ /openmsp430/trunk/doc/html/integration.html ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/serial_debug_interface.html ~ /openmsp430/trunk/doc/html/software_development_tools.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf olivier.girard Tue, 07 Jun 2011 19:10:27 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=116 Add linker script example. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=115 <div>Rev 115 - olivier.girard (1 file(s) modified)</div><div>Add linker script example.</div>+ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x olivier.girard Sun, 29 May 2011 19:41:21 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=115 Improved the VerifyCPU_ID procedure. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=114 <div>Rev 114 - olivier.girard (1 file(s) modified)</div><div>Improved the VerifyCPU_ID procedure.</div>~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl olivier.girard Thu, 26 May 2011 20:18:29 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=114 Created ChangeLog files... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=113 <div>Rev 113 - olivier.girard (2 file(s) modified)</div><div>Created ChangeLog files...</div>+ /openmsp430/trunk/ChangeLog_core.txt + /openmsp430/trunk/ChangeLog_tools.txt olivier.girard Wed, 25 May 2011 20:06:55 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=113 Modified comment. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=112 <div>Rev 112 - olivier.girard (4 file(s) modified)</div><div>Modified comment.</div>~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v olivier.girard Sat, 21 May 2011 20:39:47 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=112 Re-organized the "openMSP430_defines.v" file. ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=111 <div>Rev 111 - olivier.girard (185 file(s) modified)</div><div>Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug ...</div>~ /openmsp430/trunk/core/bench/verilog/msp_debug.v ~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v + /openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/template.def ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all + /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43 ~ /openmsp430/trunk/core/synthesis/actel/design_files.v ~ /openmsp430/trunk/core/synthesis/altera/design_files.v ~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl ~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl ~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/registers.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v + /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v ~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v ~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v ~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v + /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v + /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj olivier.girard Fri, 20 May 2011 20:39:02 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=111 Rework of the GUI for the software development tools. Added possibility ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=110 <div>Rev 110 - olivier.girard (11 file(s) modified)</div><div>Rework of the GUI for the software development tools. Added possibility ...</div>- /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.exe ~ /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.tcl - /openmsp430/trunk/tools/bin/openmsp430-loader.exe ~ /openmsp430/trunk/tools/bin/openmsp430-loader.tcl - /openmsp430/trunk/tools/bin/openmsp430-minidebug.exe ~ /openmsp430/trunk/tools/bin/openmsp430-minidebug.tcl + /openmsp430/trunk/tools/bin/README.TXT ~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl + /openmsp430/trunk/tools/lib/tcl-lib/xml.tcl + /openmsp430/trunk/tools/omsp_alias.xml ~ /openmsp430/trunk/tools/openmsp430-gdbproxy/server.tcl olivier.girard Thu, 19 May 2011 20:33:51 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=110 Update Xilinx FPGA example with the latest openMSP430 core RTL ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=109 <div>Rev 109 - olivier.girard (22 file(s) modified)</div><div>Update Xilinx FPGA example with the latest openMSP430 core RTL ...</div>~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v + /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v + /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh olivier.girard Sun, 27 Mar 2011 11:49:47 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=109 Add serial debug interface tasks to the Actel fpga simulation ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=108 <div>Rev 108 - olivier.girard (1 file(s) modified)</div><div>Add serial debug interface tasks to the Actel fpga simulation ...</div>+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/dbg_uart_tasks.v olivier.girard Fri, 25 Mar 2011 22:42:07 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=108 Update Actel and Alter FPGA examples with the latest openMSP430 ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=107 <div>Rev 107 - olivier.girard (46 file(s) modified)</div><div>Update Actel and Alter FPGA examples with the latest openMSP430 ...</div>~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v + /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v + /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/spacewar.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/prepare_implementation.tcl ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v + /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v + /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf olivier.girard Fri, 25 Mar 2011 22:41:18 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=107 Separated the Timer A defines from the openMSP430 ones. Added the ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=106 <div>Rev 106 - olivier.girard (35 file(s) modified)</div><div>Separated the Timer A defines from the openMSP430 ones. Added the ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v ~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v + /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_defines.v + /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_undefines.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v ~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile olivier.girard Fri, 25 Mar 2011 22:01:03 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=106

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