部分翻译
Error creating feed file, please check write permissions.
openmsp430
WebSVN RSS feed - openmsp430
http://opencores.com/websvn,listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&
Tue, 21 May 2013 16:26:34 +0100
FeedCreator 1.7.2
-
Update ChangeLog
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=187
<div><strong>Rev 187 - olivier.girard</strong> (1 file(s) modified)</div><div>Update ChangeLog</div>~ /openmsp430/trunk/ChangeLog_core.txt<br />
olivier.girard
Mon, 08 Apr 2013 20:01:14 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=187
-
Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=186
<div><strong>Rev 186 - olivier.girard</strong> (7 file(s) modified)</div><div>Fixed Hardware Multiplier byte operations bug: <a href="http://opencores.org/bug,assign,2247" target="_blank">http://opencores.org/bug,assign,2247</a></div>~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v<br />
olivier.girard
Mon, 08 Apr 2013 20:00:10 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=186
-
Update Altera FPGA example bitstream (no functional change... only generated ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=185
<div><strong>Rev 185 - olivier.girard</strong> (1 file(s) modified)</div><div>Update Altera FPGA example bitstream (no functional change... only generated ...</div>~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.sof<br />
olivier.girard
Sun, 07 Apr 2013 19:49:21 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=185
-
Fixed some project settings for newer Quartus version (12.1)
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=184
<div><strong>Rev 184 - olivier.girard</strong> (2 file(s) modified)</div><div>Fixed some project settings for newer Quartus version (12.1)</div>~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf<br />~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v<br />
olivier.girard
Sun, 07 Apr 2013 19:45:37 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=184
-
Update ChangeLog
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=183
<div><strong>Rev 183 - olivier.girard</strong> (1 file(s) modified)</div><div>Update ChangeLog</div>~ /openmsp430/trunk/ChangeLog_core.txt<br />
olivier.girard
Mon, 25 Feb 2013 21:36:34 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=183
-
Minor update to reflect new ASIC_CLOCKING option.
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=182
<div><strong>Rev 182 - olivier.girard</strong> (4 file(s) modified)</div><div>Minor update to reflect new ASIC_CLOCKING option.</div>~ /openmsp430/trunk/doc/html/asic_implementation.html<br />~ /openmsp430/trunk/doc/html/software_development_tools.html<br />~ /openmsp430/trunk/doc/openMSP430.odt<br />~ /openmsp430/trunk/doc/openMSP430.pdf<br />
olivier.girard
Mon, 25 Feb 2013 21:34:25 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=182
-
Update with latest oMSP Core version.
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=181
<div><strong>Rev 181 - olivier.girard</strong> (25 file(s) modified)</div><div>Update with latest oMSP Core version.</div>~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/software/bin/mifwrite<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />
olivier.girard
Mon, 25 Feb 2013 21:24:10 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=181
-
Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=180
<div><strong>Rev 180 - olivier.girard</strong> (29 file(s) modified)</div><div>Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v<br />
olivier.girard
Mon, 25 Feb 2013 21:23:18 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=180
-
Update all linker scripts with a simplified version.
Thanks to Mihai ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=179
<div><strong>Rev 179 - olivier.girard</strong> (2 file(s) modified)</div><div>Update all linker scripts with a simplified version.<br />
Thanks to Mihai ...</div>~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/linker.x<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/linker.x<br />
olivier.girard
Sat, 16 Feb 2013 21:40:09 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=179
-
Update all linker scripts with a simplified version.
Thanks to Mihai ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=178
<div><strong>Rev 178 - olivier.girard</strong> (11 file(s) modified)</div><div>Update all linker scripts with a simplified version.<br />
Thanks to Mihai ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/linker.x<br />~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/software/leds/linker.x<br />
olivier.girard
Sat, 16 Feb 2013 21:39:23 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=178
-
Update ChangeLog
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=177
<div><strong>Rev 177 - olivier.girard</strong> (1 file(s) modified)</div><div>Update ChangeLog</div>~ /openmsp430/trunk/ChangeLog_core.txt<br />
olivier.girard
Wed, 30 Jan 2013 21:24:16 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=177
-
Update FPGA projects with latest openMSP430 core RTL
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=176
<div><strong>Rev 176 - olivier.girard</strong> (19 file(s) modified)</div><div>Update FPGA projects with latest openMSP430 core RTL</div>~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/leds.bit<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/leds.mcs<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/openMSP430_fpga.bit<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />
olivier.girard
Wed, 30 Jan 2013 21:22:50 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=176
-
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=175
<div><strong>Rev 175 - olivier.girard</strong> (14 file(s) modified)</div><div>Update hardware breakpoint unit with the followings:<br />
- fixed hardware breakpoint ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br />
olivier.girard
Wed, 30 Jan 2013 21:21:42 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=175
-
Cleanup dmem_wr generation logic. Important note: this is not a ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=174
<div><strong>Rev 174 - olivier.girard</strong> (1 file(s) modified)</div><div>Cleanup dmem_wr generation logic. Important note: this is not a ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />
olivier.girard
Wed, 30 Jan 2013 21:18:42 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=174
-
Update ChangeLog
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=173
<div><strong>Rev 173 - olivier.girard</strong> (1 file(s) modified)</div><div>Update ChangeLog</div>~ /openmsp430/trunk/ChangeLog_tools.txt<br />
olivier.girard
Thu, 27 Dec 2012 23:11:42 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=173
-
GDB-Proxy now supports multi-core systems as well as hardware and ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=172
<div><strong>Rev 172 - olivier.girard</strong> (4 file(s) modified)</div><div>GDB-Proxy now supports multi-core systems as well as hardware and ...</div>~ /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.tcl<br />~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl<br />~ /openmsp430/trunk/tools/openmsp430-gdbproxy/commands.tcl<br />~ /openmsp430/trunk/tools/openmsp430-gdbproxy/server.tcl<br />
olivier.girard
Thu, 27 Dec 2012 23:06:56 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=172
-
Update in order to add Hardware breakpoint support.
Hardware breakpoint are ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=171
<div><strong>Rev 171 - olivier.girard</strong> (5 file(s) modified)</div><div>Update in order to add Hardware breakpoint support.<br />
Hardware breakpoint are ...</div>~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v<br />- /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/software/leds/gdb-target.ini<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/leds.bit<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/leds.mcs<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/openMSP430_fpga.bit<br />
olivier.girard
Thu, 27 Dec 2012 23:04:30 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=171
-
Update ChangeLog
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=170
<div><strong>Rev 170 - olivier.girard</strong> (1 file(s) modified)</div><div>Update ChangeLog</div>~ /openmsp430/trunk/ChangeLog_tools.txt<br />
olivier.girard
Thu, 06 Dec 2012 21:12:37 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=170
-
Update the Mini-debugger with multi-core support.
Up to quad core systems ...
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=169
<div><strong>Rev 169 - olivier.girard</strong> (2 file(s) modified)</div><div>Update the Mini-debugger with multi-core support.<br />
Up to quad core systems ...</div>~ /openmsp430/trunk/tools/bin/openmsp430-minidebug.tcl<br />~ /openmsp430/trunk/tools/omsp_alias.xml<br />
olivier.girard
Thu, 06 Dec 2012 21:11:29 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=169
-
Add missing second oMSP system.
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=168
<div><strong>Rev 168 - olivier.girard</strong> (1 file(s) modified)</div><div>Add missing second oMSP system.</div>+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_system_1.v<br />
olivier.girard
Thu, 06 Dec 2012 21:07:05 +0100
http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2F&rev=168
© copyright 1999-2013
OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.