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openmsp430 WebSVN RSS feed - openmsp430 http://opencores.com/websvn,listing?repname=openmsp430&path=%2Fopenmsp430%2F& Sat, 18 May 2013 21:53:25 +0100 FeedCreator 1.7.2 Modified comment. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=112 <div><strong>Rev 112 - olivier.girard</strong> (4 file(s) modified)</div><div>Modified comment.</div>~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br /> olivier.girard Sat, 21 May 2011 20:39:47 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=112 Re-organized the &quot;openMSP430_defines.v&quot; file. ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=111 <div><strong>Rev 111 - olivier.girard</strong> (185 file(s) modified)</div><div>Re-organized the &quot;openMSP430_defines.v&quot; file.<br /> Re-defined the CPU_ID register of the debug ...</div>~ /openmsp430/trunk/core/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template.def<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43<br />~ /openmsp430/trunk/core/synthesis/actel/design_files.v<br />~ /openmsp430/trunk/core/synthesis/altera/design_files.v<br />~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br />~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/registers.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v<br />+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v<br />+ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v<br />+ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj<br /> olivier.girard Fri, 20 May 2011 20:39:02 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=111 Rework of the GUI for the software development tools. Added possibility ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=110 <div><strong>Rev 110 - olivier.girard</strong> (11 file(s) modified)</div><div>Rework of the GUI for the software development tools.<br /> Added possibility ...</div>- /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.exe<br />~ /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.tcl<br />- /openmsp430/trunk/tools/bin/openmsp430-loader.exe<br />~ /openmsp430/trunk/tools/bin/openmsp430-loader.tcl<br />- /openmsp430/trunk/tools/bin/openmsp430-minidebug.exe<br />~ /openmsp430/trunk/tools/bin/openmsp430-minidebug.tcl<br />+ /openmsp430/trunk/tools/bin/README.TXT<br />~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl<br />+ /openmsp430/trunk/tools/lib/tcl-lib/xml.tcl<br />+ /openmsp430/trunk/tools/omsp_alias.xml<br />~ /openmsp430/trunk/tools/openmsp430-gdbproxy/server.tcl<br /> olivier.girard Thu, 19 May 2011 20:33:51 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=110 Update Xilinx FPGA example with the latest openMSP430 core RTL ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=109 <div><strong>Rev 109 - olivier.girard</strong> (22 file(s) modified)</div><div>Update Xilinx FPGA example with the latest openMSP430 core RTL ...</div>~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />+ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v<br />+ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh<br /> olivier.girard Sun, 27 Mar 2011 11:49:47 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=109 Add serial debug interface tasks to the Actel fpga simulation ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=108 <div><strong>Rev 108 - olivier.girard</strong> (1 file(s) modified)</div><div>Add serial debug interface tasks to the Actel fpga simulation ...</div>+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/dbg_uart_tasks.v<br /> olivier.girard Fri, 25 Mar 2011 22:42:07 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=108 Update Actel and Alter FPGA examples with the latest openMSP430 ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=107 <div><strong>Rev 107 - olivier.girard</strong> (46 file(s) modified)</div><div>Update Actel and Alter FPGA examples with the latest openMSP430 ...</div>~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v<br />+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/spacewar.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/prepare_implementation.tcl<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />+ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v<br />+ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/main.qsf<br /> olivier.girard Fri, 25 Mar 2011 22:41:18 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=107 Separated the Timer A defines from the openMSP430 ones. Added the ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=106 <div><strong>Rev 106 - olivier.girard</strong> (35 file(s) modified)</div><div>Separated the Timer A defines from the openMSP430 ones.<br /> Added the ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v<br />+ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_defines.v<br />+ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_undefines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile<br /> olivier.girard Fri, 25 Mar 2011 22:01:03 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=106 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=105 <div><strong>Rev 105 - olivier.girard</strong> (20 file(s) modified)</div><div>Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.<br /> These were ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f<br /> olivier.girard Thu, 10 Mar 2011 21:10:30 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=105 Update all FPGA example projects with the latest RTL version. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=104 <div><strong>Rev 104 - olivier.girard</strong> (71 file(s) modified)</div><div>Update all FPGA example projects with the latest RTL version.</div>~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v<br />+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/timescale.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />- /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/timescale.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v<br />+ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/timescale.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />- /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/timescale.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v<br />+ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/timescale.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/io_mux.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />- /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/timescale.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v<br /> olivier.girard Sun, 06 Mar 2011 20:02:27 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=104 Removed the timescale from all RTL files. Added possibility to exclude ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=103 <div><strong>Rev 103 - olivier.girard</strong> (24 file(s) modified)</div><div>Removed the timescale from all RTL files.<br /> Added possibility to exclude ...</div>~ /openmsp430/trunk/core/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/core/bench/verilog/ram.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />+ /openmsp430/trunk/core/bench/verilog/timescale.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v<br />- /openmsp430/trunk/core/rtl/verilog/timescale.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br /> olivier.girard Sat, 05 Mar 2011 14:44:48 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=103 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=102 <div><strong>Rev 102 - olivier.girard</strong> (3 file(s) modified)</div><div>Fixed bug reported by Mihai ( <a href="http://opencores.org/bug,view,1955" target="_blank">http://opencores.org/bug,view,1955</a> ).<br /> The following PUSH ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v<br /> olivier.girard Fri, 04 Mar 2011 22:02:09 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=102 Cosmetic change in order to prevent an X propagation whenever ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=101 <div><strong>Rev 101 - olivier.girard</strong> (2 file(s) modified)</div><div>Cosmetic change in order to prevent an X propagation whenever ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_cmp.s43<br /> olivier.girard Fri, 04 Mar 2011 20:17:50 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=101 Update HTML documentation with Actel's FPGA implementation example (file &amp; ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=100 <div><strong>Rev 100 - olivier.girard</strong> (8 file(s) modified)</div><div>Update HTML documentation with Actel's FPGA implementation example (file &amp; ...</div>~ /openmsp430/trunk/doc/html/files_directory_description.html<br />~ /openmsp430/trunk/doc/html/images/openmsp430-minidebug.png<br />+ /openmsp430/trunk/doc/html/images/spacewar.png<br />~ /openmsp430/trunk/doc/html/overview.html<br />~ /openmsp430/trunk/doc/html/software_development_tools.html<br />~ /openmsp430/trunk/doc/openMSP430.odt<br />~ /openmsp430/trunk/doc/openMSP430.pdf<br />~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest<br /> olivier.girard Tue, 01 Mar 2011 21:15:13 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=100 Small fix for CVER simulator support. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=99 <div><strong>Rev 99 - olivier.girard</strong> (2 file(s) modified)</div><div>Small fix for CVER simulator support.</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br /> olivier.girard Mon, 28 Feb 2011 20:26:17 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=99 Added support for VCS verilog simulator. VPD and TRN waveforms can ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=98 <div><strong>Rev 98 - olivier.girard</strong> (13 file(s) modified)</div><div>Added support for VCS verilog simulator.<br /> VPD and TRN waveforms can ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/rtlsim.sh<br /> olivier.girard Mon, 28 Feb 2011 20:20:51 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=98 Update Tools' Windows executables with EraseROM command fix. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=97 <div><strong>Rev 97 - olivier.girard</strong> (3 file(s) modified)</div><div>Update Tools' Windows executables with EraseROM command fix.</div>~ /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.exe<br />~ /openmsp430/trunk/tools/bin/openmsp430-loader.exe<br />~ /openmsp430/trunk/tools/bin/openmsp430-minidebug.exe<br /> olivier.girard Sun, 27 Feb 2011 20:36:15 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=97 Fixed EraseROM command in the TCL library of the Software ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=96 <div><strong>Rev 96 - olivier.girard</strong> (6 file(s) modified)</div><div>Fixed EraseROM command in the TCL library of the Software ...</div>- /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.a43<br />- /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.bin<br />- /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.elf<br />- /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.lst<br />- /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/memledtest.mif<br />~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl<br /> olivier.girard Sun, 27 Feb 2011 20:29:35 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=96 Update some test patterns for the additional simulator supports. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=95 <div><strong>Rev 95 - olivier.girard</strong> (4 file(s) modified)</div><div>Update some test patterns for the additional simulator supports.</div>~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v<br /> olivier.girard Thu, 24 Feb 2011 20:37:57 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=95 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support ... http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=94 <div><strong>Rev 94 - olivier.girard</strong> (13 file(s) modified)</div><div>Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support ...</div>~ /openmsp430/trunk/core/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/core/bench/verilog/registers.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/rtlsim.sh<br /> olivier.girard Thu, 24 Feb 2011 20:33:35 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=94 Update Tools' Windows executables. http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=93 <div><strong>Rev 93 - olivier.girard</strong> (3 file(s) modified)</div><div>Update Tools' Windows executables.</div>~ /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.exe<br />~ /openmsp430/trunk/tools/bin/openmsp430-loader.exe<br />~ /openmsp430/trunk/tools/bin/openmsp430-minidebug.exe<br /> olivier.girard Sun, 20 Feb 2011 21:06:09 +0100 http://opencores.com/websvn,revision?repname=openmsp430&path=%2Fopenmsp430%2F&rev=93
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