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http://opencores.com/websvn,listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&
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http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=338
<div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br />rootTue, 05 May 2009 15:18:25 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=338New directory structure.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=335
<div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br />rootMon, 09 Mar 2009 10:03:10 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=335This commit was manufactured by cvs2svn to create tag 'rel_4'.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=151
<div><strong>Rev 151 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_4'.</div>+ /tags/rel_4<br />Wed, 04 Sep 2002 18:47:58 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=151Debug registers reg1, 2, 3, 4 connected. Synchronization of many ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=150
<div><strong>Rev 150 - mohor</strong> (1 file(s) modified)</div><div>Debug registers reg1, 2, 3, 4 connected. Synchronization of many ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />mohorWed, 04 Sep 2002 18:47:57 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=150Signals related to the control frames connected. Debug registers reg1, ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=149
<div><strong>Rev 149 - mohor</strong> (1 file(s) modified)</div><div>Signals related to the control frames connected. Debug registers reg1, ...</div>~ /trunk/rtl/verilog/eth_top.v<br />mohorWed, 04 Sep 2002 18:44:10 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=149Bug when last byte of destination address was not checked ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=148
<div><strong>Rev 148 - mohor</strong> (1 file(s) modified)</div><div>Bug when last byte of destination address was not checked ...</div>~ /trunk/rtl/verilog/eth_rxaddrcheck.v<br />mohorWed, 04 Sep 2002 18:41:06 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=148ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=147
<div><strong>Rev 147 - mohor</strong> (1 file(s) modified)</div><div>ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to<br />
the control frames ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />mohorWed, 04 Sep 2002 18:40:25 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=147CarrierSenseLost status is not set when working in loopback mode.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=146
<div><strong>Rev 146 - mohor</strong> (1 file(s) modified)</div><div>CarrierSenseLost status is not set when working in loopback mode.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />mohorWed, 04 Sep 2002 18:38:03 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=146Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=145
<div><strong>Rev 145 - mohor</strong> (1 file(s) modified)</div><div>Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).</div>~ /trunk/rtl/verilog/eth_defines.v<br />mohorWed, 04 Sep 2002 18:36:49 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=145Only values smaller or equal to 0x80 can be written ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=143
<div><strong>Rev 143 - mohor</strong> (1 file(s) modified)</div><div>Only values smaller or equal to 0x80 can be written ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />mohorMon, 19 Aug 2002 16:01:40 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=143Syntax error fixed.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=141
<div><strong>Rev 141 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br />mohorFri, 16 Aug 2002 22:28:23 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=141Syntax error fixed.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=140
<div><strong>Rev 140 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br />mohorFri, 16 Aug 2002 22:23:03 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=140Synchronous reset added to all registers. Defines used for width. ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=139
<div><strong>Rev 139 - mohor</strong> (1 file(s) modified)</div><div>Synchronous reset added to all registers. Defines used for width. ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />mohorFri, 16 Aug 2002 22:14:22 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=139Synchronous reset added.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=138
<div><strong>Rev 138 - mohor</strong> (1 file(s) modified)</div><div>Synchronous reset added.</div>~ /trunk/rtl/verilog/eth_register.v<br />mohorFri, 16 Aug 2002 22:10:12 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=138Defines for register width added. mii_rst signal in MIIMODER register
changed.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=137
<div><strong>Rev 137 - mohor</strong> (1 file(s) modified)</div><div>Defines for register width added. mii_rst signal in MIIMODER register<br />
changed.</div>~ /trunk/rtl/verilog/eth_defines.v<br />mohorFri, 16 Aug 2002 22:09:47 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=137Parameter ResetValue changed to capital letters.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=136
<div><strong>Rev 136 - mohor</strong> (1 file(s) modified)</div><div>Parameter ResetValue changed to capital letters.</div>~ /trunk/rtl/verilog/eth_register.v<br />mohorFri, 16 Aug 2002 12:33:27 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=136New revision. External DMA removed, TX_BD_NUM changed.
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=135
<div><strong>Rev 135 - mohor</strong> (2 file(s) modified)</div><div>New revision. External DMA removed, TX_BD_NUM changed.</div>~ /trunk/doc/eth_speci.pdf<br />~ /trunk/doc/src/eth_speci.doc<br />mohorWed, 14 Aug 2002 20:41:57 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=135Register TX_BD_NUM is changed so it contains value of the ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=134
<div><strong>Rev 134 - mohor</strong> (2 file(s) modified)</div><div>Register TX_BD_NUM is changed so it contains value of the ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />mohorWed, 14 Aug 2002 19:31:48 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=134- Busy signal was not set on time when scan ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=133
<div><strong>Rev 133 - mohor</strong> (1 file(s) modified)</div><div>- Busy signal was not set on time when scan ...</div>~ /trunk/rtl/verilog/eth_miim.v<br />mohorWed, 14 Aug 2002 18:32:10 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=133LinkFailRegister is reflecting the status of the PHY's link fail ...
http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=132
<div><strong>Rev 132 - mohor</strong> (1 file(s) modified)</div><div>LinkFailRegister is reflecting the status of the PHY's link fail ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />mohorWed, 14 Aug 2002 18:26:37 +0100http://opencores.com/websvn,revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=132
