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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] - Rev 59

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Last modification

  • Rev 59, 2010-02-01 23:12:28 GMT
  • Author: olivier.girard
  • Log message:
    Update the FPGA projects with the latest core design updates.

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