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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] - Rev 111

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Last modification

  • Rev 111, 2011-05-20 20:39:02 GMT
  • Author: olivier.girard
  • Log message:
    Re-organized the "openMSP430_defines.v" file.
    Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
    Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
    As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
Path
/openmsp430/trunk/core/bench/verilog/msp_debug.v
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/omsp_alu.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
/openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
/openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
/openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/bin/template.def
/openmsp430/trunk/core/sim/rtl_sim/run/run
/openmsp430/trunk/core/sim/rtl_sim/run/run_all
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
/openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43
/openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.v
/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
/openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43
/openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43
/openmsp430/trunk/core/synthesis/actel/design_files.v
/openmsp430/trunk/core/synthesis/altera/design_files.v
/openmsp430/trunk/core/synthesis/synopsys/constraints.tcl
/openmsp430/trunk/core/synthesis/synopsys/read.tcl
/openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/registers.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v
/openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v
/openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v
/openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_cell.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_cell.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj

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