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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] - Rev 109

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Last modification

  • Rev 109, 2011-03-27 11:49:47 GMT
  • Author: olivier.girard
  • Log message:
    Update Xilinx FPGA example with the latest openMSP430 core RTL version.
Path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh

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