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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] - Rev 80

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Last modification

  • Rev 80, 2010-12-05 13:23:31 GMT
  • Author: olivier.girard
  • Log message:
    Create initial version of the Actel FPGA implementation example.
Path
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/DAC121S101.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/proasic3l.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/registers.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/doc
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/doc/M1A3PL_DEV_KIT_QS.pdf
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/doc/M1IGLOO_StarterKit_v1_5_UG.pdf
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/timescale.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/dmem_128B.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/pmem_2kB.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/ihex2mem.tcl
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/run
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/run/run
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/run/run_disassemble
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/spacewar.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/bzsin.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/cline.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/compar.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/explode.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/hardware.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/main.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/makefile
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/point.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/reset.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/rocket1.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/rocket2.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/score.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/spacewar.h
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/update.c
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/build_fpga.tcl
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.pdc
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.sdc
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/libero_designer.tcl
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/synplify.tcl

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