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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 74

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Last modification

  • Rev 74, 2010-08-28 19:53:08 GMT
  • Author: olivier.girard
  • Log message:
    Update serial debug interface to support memories with a size which is not a power of 2.
    Update the software tools accordingly.
Path
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
/openmsp430/trunk/doc/html/overview.html
/openmsp430/trunk/doc/html/serial_debug_interface.html
/openmsp430/trunk/doc/openMSP430.odt
/openmsp430/trunk/doc/openMSP430.pdf
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl

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