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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 141

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Last modification

  • Rev 141, 2012-05-05 21:22:06 GMT
  • Author: olivier.girard
  • Log message:
    Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later)
Path
/openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
/openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/main.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/omsp_system.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/periph.x
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.s43
/openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.s43
/openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43
/openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.s43
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.s43
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.s43
/openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.s43
/openmsp430/trunk/core/sim/rtl_sim/src/nmi.s43
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sandbox.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43
/openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43
/openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.s43

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