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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 134

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Last modification

  • Rev 134, 2012-03-22 20:31:06 GMT
  • Author: olivier.girard
  • Log message:
    Add full ASIC support (low-power modes, DFT, ...).
    Improved serial debug interface reliability.
Path
/openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v
/openmsp430/trunk/core/bench/verilog/msp_debug.v
/openmsp430/trunk/core/bench/verilog/registers.v
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/omsp_alu.v
/openmsp430/trunk/core/rtl/verilog/omsp_and_gate.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_gate.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
/openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
/openmsp430/trunk/core/rtl/verilog/omsp_scan_mux.v
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
/openmsp430/trunk/core/rtl/verilog/omsp_sync_reset.v
/openmsp430/trunk/core/rtl/verilog/omsp_wakeup_cell.v
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
/openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude.dat
/openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude_bits.dat
/openmsp430/trunk/core/sim/rtl_sim/bin/cov_iccr_merge.cf
/openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.ccf
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/template.def
/openmsp430/trunk/core/sim/rtl_sim/bin/template.x
/openmsp430/trunk/core/sim/rtl_sim/run/load_waveform.sav
/openmsp430/trunk/core/sim/rtl_sim/run/run
/openmsp430/trunk/core/sim/rtl_sim/run/run_all
/openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy
/openmsp430/trunk/core/sim/rtl_sim/run/run_c
/openmsp430/trunk/core/sim/rtl_sim/run/run_coverage_analysis
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/main.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/periph.x
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v
/openmsp430/trunk/core/sim/rtl_sim/src/core.f
/openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/nmi.s43
/openmsp430/trunk/core/sim/rtl_sim/src/nmi.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/scan.s43
/openmsp430/trunk/core/sim/rtl_sim/src/scan.v
/openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sfr.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
/openmsp430/trunk/core/sim/rtl_sim/src/submit.prj
/openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v
/openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.s43
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v
/openmsp430/trunk/core/synthesis/altera/design_files.v
/openmsp430/trunk/core/synthesis/synopsys/constraints.tcl
/openmsp430/trunk/core/synthesis/synopsys/read.tcl
/openmsp430/trunk/core/synthesis/synopsys/run_tmax
/openmsp430/trunk/core/synthesis/synopsys/synthesis.tcl
/openmsp430/trunk/core/synthesis/synopsys/tmax.tcl
/openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj

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