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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 106

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Last modification

  • Rev 106, 2011-03-25 22:01:03 GMT
  • Author: olivier.girard
  • Log message:
    Separated the Timer A defines from the openMSP430 ones.
    Added the "dbg_en" port in order to allow a separate reset of the debug interface.
    Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
    Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
    Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
Path
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
/openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_defines.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA_undefines.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
/openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl
/openmsp430/trunk/core/sim/rtl_sim/run/run
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile

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