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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] - Rev 23

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Last modification

  • Rev 23, 2009-08-30 16:39:26 GMT
  • Author: olivier.girard
  • Log message:
    Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
    In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
Path
/openmsp430/trunk/core/bench/verilog/msp_debug.v
/openmsp430/trunk/core/bench/verilog/ram.v
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/alu.v
/openmsp430/trunk/core/rtl/verilog/clock_module.v
/openmsp430/trunk/core/rtl/verilog/dbg.v
/openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
/openmsp430/trunk/core/rtl/verilog/dbg_uart.v
/openmsp430/trunk/core/rtl/verilog/execution_unit.v
/openmsp430/trunk/core/rtl/verilog/frontend.v
/openmsp430/trunk/core/rtl/verilog/mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.inc
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/periph/gpio.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
/openmsp430/trunk/core/rtl/verilog/periph/timerA.v
/openmsp430/trunk/core/rtl/verilog/register_file.v
/openmsp430/trunk/core/rtl/verilog/sfr.v
/openmsp430/trunk/core/rtl/verilog/timescale.v
/openmsp430/trunk/core/rtl/verilog/watchdog.v
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
/openmsp430/trunk/doc/html/core.html
/openmsp430/trunk/doc/html/files_directory_description.html
/openmsp430/trunk/doc/html/serial_debug_interface.html
/openmsp430/trunk/doc/openMSP430.odt
/openmsp430/trunk/doc/openMSP430.pdf
/openmsp430/trunk/fpga/diligent_s3board/bench/verilog/msp_debug.v
/openmsp430/trunk/fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/driver_7segment.v
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/io_mux.v
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openMSP430.inc
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/timescale.v
/openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v

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