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[/] [openmsp430/] [trunk/] - Rev 121

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Last modification

  • Rev 121, 2011-07-25 20:11:04 GMT
  • Author: olivier.girard
  • Log message:
    Add a new FPGA example for the LX9 Microboard from Avnet.
    Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)
Path
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/msp430f1121a.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/hardware.h
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/main.c
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/hello/Makefile
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/hardware.h
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/main.c
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/Makefile
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/README.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.h
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/swuart.s
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/firmware/ta_uart/ta_uart.lst
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/openmsp430.xise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.bit
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/openMSP430_fpga.ucf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/blk_mem_gen_v6_2_readme.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.asy
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.gise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.ngc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.veo
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xco
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon.xise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_flist.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_readme.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_icon_xmdf.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.asy
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.cdc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ejp
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.gise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.ngc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.veo
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xco
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila.xise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_flist.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_readme.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/chipscope_ila_xmdf.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.cgp
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/coregen.log
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.asy
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.gise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.ngc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.veo
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xco
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512.xise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_flist.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/ram_8x512_xmdf.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.asy
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.gise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.ngc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.veo
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xco
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k.xise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_flist.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/rom_8x2k_xmdf.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/coregen/summary.log
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/io_mux.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_alu.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_dbg_uart.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_execution_unit.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_frontend.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_multiplier.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_register_file.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sfr.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_sync_cell.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/openMSP430_undefines.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_gpio.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/omsp_timerA_undefines.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_8b.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openmsp430/periph/template_periph_16b.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/ise/rtl/verilog/openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/README

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