OpenCores

Subversion Repositories pairing

[/] - Rev 28

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 792d 10h /
27 definition for undefined wire homer.xing 792d 10h /
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 798d 06h /
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 798d 07h /
24 LGPL claim in each source hdl file homer.xing 806d 07h /
23 LGPL license text homer.xing 806d 07h /
22 Change TAB to space homer.xing 806d 08h /
21 Add detailed input data capture condition in the document homer.xing 806d 09h /
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 807d 11h /
19 Update synthesis result homer.xing 808d 04h /
18 add synthesis result homer.xing 808d 04h /
17 use logic for $f3m_mux6$ homer.xing 808d 06h /
16 Add synthesis configuration files homer.xing 808d 09h /
15 add document. ha ha ha homer.xing 808d 10h /
14 Move constraint file homer.xing 808d 11h /
13 Add document and synthesis directories homer.xing 808d 11h /
12 Simplify the interface of the core. homer.xing 808d 12h /
11 Cheers! as fast as a rocket homer.xing 809d 07h /
10 Ho ho, better circuit homer.xing 810d 01h /
9 Add constrains file for ISE homer.xing 811d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.