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Rev Log message Author Age Path
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 1452d 18h /
27 definition for undefined wire homer.xing 1452d 18h /
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 1458d 15h /
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 1458d 15h /
24 LGPL claim in each source hdl file homer.xing 1466d 15h /
23 LGPL license text homer.xing 1466d 15h /
22 Change TAB to space homer.xing 1466d 16h /
21 Add detailed input data capture condition in the document homer.xing 1466d 17h /
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 1467d 19h /
19 Update synthesis result homer.xing 1468d 12h /
18 add synthesis result homer.xing 1468d 12h /
17 use logic for $f3m_mux6$ homer.xing 1468d 14h /
16 Add synthesis configuration files homer.xing 1468d 17h /
15 add document. ha ha ha homer.xing 1468d 18h /
14 Move constraint file homer.xing 1468d 19h /
13 Add document and synthesis directories homer.xing 1468d 19h /
12 Simplify the interface of the core. homer.xing 1468d 20h /
11 Cheers! as fast as a rocket homer.xing 1469d 15h /
10 Ho ho, better circuit homer.xing 1470d 09h /
9 Add constrains file for ISE homer.xing 1471d 13h /

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