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28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 988d 01h /
27 definition for undefined wire homer.xing 988d 01h /
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 993d 21h /
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 993d 21h /
24 LGPL claim in each source hdl file homer.xing 1001d 21h /
23 LGPL license text homer.xing 1001d 22h /
22 Change TAB to space homer.xing 1001d 23h /
21 Add detailed input data capture condition in the document homer.xing 1001d 23h /
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 1003d 02h /
19 Update synthesis result homer.xing 1003d 19h /
18 add synthesis result homer.xing 1003d 19h /
17 use logic for $f3m_mux6$ homer.xing 1003d 21h /
16 Add synthesis configuration files homer.xing 1004d 00h /
15 add document. ha ha ha homer.xing 1004d 01h /
14 Move constraint file homer.xing 1004d 01h /
13 Add document and synthesis directories homer.xing 1004d 02h /
12 Simplify the interface of the core. homer.xing 1004d 02h /
11 Cheers! as fast as a rocket homer.xing 1004d 22h /
10 Ho ho, better circuit homer.xing 1005d 16h /
9 Add constrains file for ISE homer.xing 1006d 20h /

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