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Rev Log message Author Age Path
22 Change TAB to space homer.xing 1470d 06h /pairing/
21 Add detailed input data capture condition in the document homer.xing 1470d 06h /pairing/
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 1471d 08h /pairing/
19 Update synthesis result homer.xing 1472d 02h /pairing/
18 add synthesis result homer.xing 1472d 02h /pairing/
17 use logic for $f3m_mux6$ homer.xing 1472d 03h /pairing/
16 Add synthesis configuration files homer.xing 1472d 06h /pairing/
15 add document. ha ha ha homer.xing 1472d 08h /pairing/
14 Move constraint file homer.xing 1472d 08h /pairing/
13 Add document and synthesis directories homer.xing 1472d 08h /pairing/
12 Simplify the interface of the core. homer.xing 1472d 09h /pairing/
11 Cheers! as fast as a rocket homer.xing 1473d 05h /pairing/
10 Ho ho, better circuit homer.xing 1473d 23h /pairing/
9 Add constrains file for ISE homer.xing 1475d 02h /pairing/
8 Finished Tate Pairing. Ha ha ha homer.xing 1475d 03h /pairing/
7 Finish inversion @ f33m homer.xing 1483d 08h /pairing/
6 add testbench for $f33m$. homer.xing 1484d 08h /pairing/
5 rename director : verilog/ -> rtl/ homer.xing 1484d 08h /pairing/
4 add testbench homer.xing 1485d 06h /pairing/
3 finish Duursma Lee algorithm. doing f33m module homer.xing 1485d 06h /pairing/

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