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Rev Log message Author Age Path
33 new email & English name of the author homer.xing 1434d 18h /pairing/
32 changed surname: Xing -> Hsing. homer.xing 1434d 19h /pairing/
31 accurate source code copyright comment header homer.xing 1434d 19h /pairing/
30 LGPL header homer.xing 1444d 23h /pairing/
29 default net type is wire homer.xing 1451d 19h /pairing/
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 1451d 22h /pairing/
27 definition for undefined wire homer.xing 1451d 23h /pairing/
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 1457d 19h /pairing/
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 1457d 19h /pairing/
24 LGPL claim in each source hdl file homer.xing 1465d 19h /pairing/
23 LGPL license text homer.xing 1465d 19h /pairing/
22 Change TAB to space homer.xing 1465d 21h /pairing/
21 Add detailed input data capture condition in the document homer.xing 1465d 21h /pairing/
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 1466d 23h /pairing/
19 Update synthesis result homer.xing 1467d 16h /pairing/
18 add synthesis result homer.xing 1467d 17h /pairing/
17 use logic for $f3m_mux6$ homer.xing 1467d 18h /pairing/
16 Add synthesis configuration files homer.xing 1467d 21h /pairing/
15 add document. ha ha ha homer.xing 1467d 22h /pairing/
14 Move constraint file homer.xing 1467d 23h /pairing/

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