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Rev Log message Author Age Path
33 new email & English name of the author homer.xing 965d 20h /pairing/
32 changed surname: Xing -> Hsing. homer.xing 965d 21h /pairing/
31 accurate source code copyright comment header homer.xing 965d 21h /pairing/
30 LGPL header homer.xing 976d 01h /pairing/
29 default net type is wire homer.xing 982d 22h /pairing/
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 983d 00h /pairing/
27 definition for undefined wire homer.xing 983d 01h /pairing/
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 988d 21h /pairing/
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 988d 21h /pairing/
24 LGPL claim in each source hdl file homer.xing 996d 21h /pairing/
23 LGPL license text homer.xing 996d 21h /pairing/
22 Change TAB to space homer.xing 996d 23h /pairing/
21 Add detailed input data capture condition in the document homer.xing 996d 23h /pairing/
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 998d 01h /pairing/
19 Update synthesis result homer.xing 998d 19h /pairing/
18 add synthesis result homer.xing 998d 19h /pairing/
17 use logic for $f3m_mux6$ homer.xing 998d 20h /pairing/
16 Add synthesis configuration files homer.xing 999d 00h /pairing/
15 add document. ha ha ha homer.xing 999d 01h /pairing/
14 Move constraint file homer.xing 999d 01h /pairing/

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