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Rev Log message Author Age Path
199 Update ChangeLog olivier.girard 14d 06h /
198 Update GDB-Proxy to support new GCC/GDB compiler version from RedHat/TI olivier.girard 14d 06h /
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 265d 05h /
196 Update ChangeLog olivier.girard 308d 04h /
195 Update HTML documentation with configurable number of IRQ option. olivier.girard 308d 04h /
194 Update PDF and ODT documentation. olivier.girard 308d 05h /
193 Update FPGA projects with latest core RTL changes. olivier.girard 308d 05h /
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 308d 05h /
191 Update ChangeLog olivier.girard 448d 05h /
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 448d 05h /
189 Update ChangeLog olivier.girard 460d 05h /
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 460d 05h /
187 Update ChangeLog olivier.girard 561d 05h /
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 561d 05h /
185 Update Altera FPGA example bitstream (no functional change... only generated with a newer Quartus version) olivier.girard 562d 05h /
184 Fixed some project settings for newer Quartus version (12.1) olivier.girard 562d 05h /
183 Update ChangeLog olivier.girard 603d 04h /
182 Minor update to reflect new ASIC_CLOCKING option. olivier.girard 603d 04h /
181 Update with latest oMSP Core version. olivier.girard 603d 04h /
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)
olivier.girard 603d 04h /

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