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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Rev 202


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202 Add DMA interface support + LINT cleanup olivier.girard 98d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
193 Update FPGA projects with latest core RTL changes. olivier.girard 659d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
181 Update with latest oMSP Core version. olivier.girard 954d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 1087d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
136 Update all FPGA projects with the latest core version. olivier.girard 1294d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1601d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 1656d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.
olivier.girard 1866d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
72 Expand configurability options of the program and data memory sizes. olivier.girard 1893d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 2040d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
59 Update the FPGA projects with the latest core design updates. olivier.girard 2074d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
37 olivier.girard 2108d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.
olivier.girard 2108d 22h /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v

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