OpenCores

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.s43] - Rev 141

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 845d 04h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1196d 04h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1252d 03h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
19 added SVN property for keywords olivier.girard 1850d 03h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
18 Updated headers with SVN info olivier.girard 1850d 03h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43
2 Upload complete openMSP430 project to the SVN repository olivier.girard 1885d 03h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.