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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [run] - Rev 33


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33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.
olivier.girard 2236d 10h /openmsp430/trunk/core/sim/rtl_sim/run
6 Some more SVN ignore properties... olivier.girard 2405d 08h /openmsp430/trunk/core/sim/rtl_sim/run
2 Upload complete openMSP430 project to the SVN repository olivier.girard 2418d 07h /openmsp430/trunk/core/sim/rtl_sim/run

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