OpenCores

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] - Rev 192

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 344d 13h /openmsp430/trunk/core/rtl/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 484d 13h /openmsp430/trunk/core/rtl/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 496d 12h /openmsp430/trunk/core/rtl/
186 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 olivier.girard 597d 13h /openmsp430/trunk/core/rtl/
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)
olivier.girard 639d 12h /openmsp430/trunk/core/rtl/
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.
olivier.girard 665d 12h /openmsp430/trunk/core/rtl/
174 Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. olivier.girard 665d 12h /openmsp430/trunk/core/rtl/
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 772d 12h /openmsp430/trunk/core/rtl/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 857d 11h /openmsp430/trunk/core/rtl/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 860d 13h /openmsp430/trunk/core/rtl/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 979d 12h /openmsp430/trunk/core/rtl/
132 Update FPGA examples with the POP.B bug fix olivier.girard 992d 12h /openmsp430/trunk/core/rtl/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 1000d 11h /openmsp430/trunk/core/rtl/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 1076d 12h /openmsp430/trunk/core/rtl/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 1252d 13h /openmsp430/trunk/core/rtl/
112 Modified comment. olivier.girard 1285d 12h /openmsp430/trunk/core/rtl/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1286d 12h /openmsp430/trunk/core/rtl/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1342d 11h /openmsp430/trunk/core/rtl/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1357d 12h /openmsp430/trunk/core/rtl/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 1362d 18h /openmsp430/trunk/core/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.