Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] - Rev 205


Filtering Options

Clear current filter

Rev Log message Author Age Path
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).
olivier.girard 14d 15h /openmsp430/trunk/core/rtl/
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 21d 15h /openmsp430/trunk/core/rtl/
202 Add DMA interface support + LINT cleanup olivier.girard 28d 14h /openmsp430/trunk/core/rtl/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 189d 14h /openmsp430/trunk/core/rtl/
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 589d 15h /openmsp430/trunk/core/rtl/
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 729d 15h /openmsp430/trunk/core/rtl/
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 741d 15h /openmsp430/trunk/core/rtl/
186 Fixed Hardware Multiplier byte operations bug:,assign,2247 olivier.girard 842d 16h /openmsp430/trunk/core/rtl/
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)
olivier.girard 884d 14h /openmsp430/trunk/core/rtl/
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.
olivier.girard 910d 14h /openmsp430/trunk/core/rtl/
174 Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. olivier.girard 910d 14h /openmsp430/trunk/core/rtl/
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 1017d 15h /openmsp430/trunk/core/rtl/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 1102d 13h /openmsp430/trunk/core/rtl/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request,view,2171 (burst accesses through the serial debug interface)
olivier.girard 1105d 15h /openmsp430/trunk/core/rtl/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 1224d 15h /openmsp430/trunk/core/rtl/
132 Update FPGA examples with the POP.B bug fix olivier.girard 1237d 15h /openmsp430/trunk/core/rtl/
130 Fixed POP.B bug (see Bugtracker,assign,2137 ) olivier.girard 1245d 14h /openmsp430/trunk/core/rtl/
128 Fixed CALL x(SR) bug (see Bugtracker,view,2111 ) olivier.girard 1321d 15h /openmsp430/trunk/core/rtl/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 1497d 16h /openmsp430/trunk/core/rtl/
112 Modified comment. olivier.girard 1530d 15h /openmsp430/trunk/core/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2015, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.