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Rev Log message Author Age Path
142 Beautify the linker script examples. olivier.girard 1297d 20h /openmsp430/trunk/core/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 1301d 19h /openmsp430/trunk/core/
139 Add some SVN ignore patterns olivier.girard 1314d 05h /openmsp430/trunk/core/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 1314d 05h /openmsp430/trunk/core/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 1345d 20h /openmsp430/trunk/core/
132 Update FPGA examples with the POP.B bug fix olivier.girard 1358d 19h /openmsp430/trunk/core/
130 Fixed POP.B bug (see Bugtracker,assign,2137 ) olivier.girard 1366d 18h /openmsp430/trunk/core/
128 Fixed CALL x(SR) bug (see Bugtracker,view,2111 ) olivier.girard 1442d 19h /openmsp430/trunk/core/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 1514d 20h /openmsp430/trunk/core/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 1618d 21h /openmsp430/trunk/core/
115 Add linker script example. olivier.girard 1643d 20h /openmsp430/trunk/core/
112 Modified comment. olivier.girard 1651d 19h /openmsp430/trunk/core/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1652d 19h /openmsp430/trunk/core/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1708d 18h /openmsp430/trunk/core/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1723d 19h /openmsp430/trunk/core/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 1729d 01h /openmsp430/trunk/core/
102 Fixed bug reported by Mihai (,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+
olivier.girard 1729d 18h /openmsp430/trunk/core/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 1729d 20h /openmsp430/trunk/core/
99 Small fix for CVER simulator support. olivier.girard 1733d 20h /openmsp430/trunk/core/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.
olivier.girard 1733d 20h /openmsp430/trunk/core/

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