OpenCores

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] - Rev 142

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
142 Beautify the linker script examples. olivier.girard 895d 17h /openmsp430/trunk/core/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 899d 16h /openmsp430/trunk/core/
139 Add some SVN ignore patterns olivier.girard 912d 02h /openmsp430/trunk/core/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 912d 02h /openmsp430/trunk/core/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 943d 17h /openmsp430/trunk/core/
132 Update FPGA examples with the POP.B bug fix olivier.girard 956d 17h /openmsp430/trunk/core/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 964d 16h /openmsp430/trunk/core/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 1040d 16h /openmsp430/trunk/core/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 1112d 17h /openmsp430/trunk/core/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 1216d 18h /openmsp430/trunk/core/
115 Add linker script example. olivier.girard 1241d 18h /openmsp430/trunk/core/
112 Modified comment. olivier.girard 1249d 17h /openmsp430/trunk/core/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1250d 17h /openmsp430/trunk/core/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1306d 15h /openmsp430/trunk/core/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1321d 16h /openmsp430/trunk/core/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 1326d 23h /openmsp430/trunk/core/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+
olivier.girard 1327d 15h /openmsp430/trunk/core/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 1327d 17h /openmsp430/trunk/core/
99 Small fix for CVER simulator support. olivier.girard 1331d 17h /openmsp430/trunk/core/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.
olivier.girard 1331d 17h /openmsp430/trunk/core/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.