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114 Improved the VerifyCPU_ID procedure. olivier.girard 1253d 07h /openmsp430/trunk/
113 Created ChangeLog files... olivier.girard 1254d 07h /openmsp430/trunk/
112 Modified comment. olivier.girard 1258d 07h /openmsp430/trunk/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1259d 07h /openmsp430/trunk/
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.
olivier.girard 1260d 07h /openmsp430/trunk/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 1313d 16h /openmsp430/trunk/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 1315d 05h /openmsp430/trunk/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 1315d 05h /openmsp430/trunk/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1315d 06h /openmsp430/trunk/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1330d 06h /openmsp430/trunk/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 1334d 07h /openmsp430/trunk/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 1335d 13h /openmsp430/trunk/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+
olivier.girard 1336d 06h /openmsp430/trunk/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 1336d 07h /openmsp430/trunk/
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 1339d 06h /openmsp430/trunk/
99 Small fix for CVER simulator support. olivier.girard 1340d 07h /openmsp430/trunk/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.
olivier.girard 1340d 07h /openmsp430/trunk/
97 Update Tools' Windows executables with EraseROM command fix. olivier.girard 1341d 07h /openmsp430/trunk/
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 1341d 07h /openmsp430/trunk/
95 Update some test patterns for the additional simulator supports. olivier.girard 1344d 07h /openmsp430/trunk/

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