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114 Improved the VerifyCPU_ID procedure. olivier.girard 1063d 18h /openmsp430/
113 Created ChangeLog files... olivier.girard 1064d 18h /openmsp430/
112 Modified comment. olivier.girard 1068d 17h /openmsp430/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1069d 17h /openmsp430/
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.
olivier.girard 1070d 17h /openmsp430/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 1124d 02h /openmsp430/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 1125d 15h /openmsp430/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 1125d 15h /openmsp430/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1125d 16h /openmsp430/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1140d 17h /openmsp430/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 1144d 18h /openmsp430/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 1145d 23h /openmsp430/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+
olivier.girard 1146d 16h /openmsp430/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 1146d 18h /openmsp430/
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 1149d 17h /openmsp430/
99 Small fix for CVER simulator support. olivier.girard 1150d 17h /openmsp430/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.
olivier.girard 1150d 18h /openmsp430/
97 Update Tools' Windows executables with EraseROM command fix. olivier.girard 1151d 17h /openmsp430/
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 1151d 17h /openmsp430/
95 Update some test patterns for the additional simulator supports. olivier.girard 1154d 17h /openmsp430/

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