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Rev Log message Author Age Path
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 758d 16h /
133 Add support for new CPU version. olivier.girard 758d 16h /
132 Update FPGA examples with the POP.B bug fix olivier.girard 771d 16h /
131 Update ChangeLog olivier.girard 779d 15h /
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 779d 15h /
129 Update ChangeLog olivier.girard 855d 16h /
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 855d 16h /
127 update changelog... olivier.girard 891d 15h /
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.
olivier.girard 891d 15h /
125 update changelog... olivier.girard 905d 18h /
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.
olivier.girard 906d 05h /
123 update changelog... olivier.girard 927d 16h /
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 927d 16h /
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)
olivier.girard 999d 17h /
120 update tools changelog... olivier.girard 1031d 00h /
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 1031d 00h /
118 Changelog update (move to modified BSD license). olivier.girard 1031d 17h /
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 1031d 17h /
116 Update documentation to reflect the latest core updates. olivier.girard 1047d 18h /
115 Add linker script example. olivier.girard 1056d 17h /
114 Improved the VerifyCPU_ID procedure. olivier.girard 1059d 17h /
113 Created ChangeLog files... olivier.girard 1060d 17h /
112 Modified comment. olivier.girard 1064d 16h /
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1065d 16h /
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.
olivier.girard 1066d 16h /
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 1120d 01h /
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 1121d 14h /
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 1121d 14h /
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1121d 15h /
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1136d 16h /

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