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Rev Log message Author Age Path
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 1045d 20h /
133 Add support for new CPU version. olivier.girard 1045d 20h /
132 Update FPGA examples with the POP.B bug fix olivier.girard 1058d 19h /
131 Update ChangeLog olivier.girard 1066d 18h /
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 1066d 18h /
129 Update ChangeLog olivier.girard 1142d 19h /
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 1142d 19h /
127 update changelog... olivier.girard 1178d 18h /
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.
olivier.girard 1178d 18h /
125 update changelog... olivier.girard 1192d 22h /
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.
olivier.girard 1193d 09h /
123 update changelog... olivier.girard 1214d 20h /
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 1214d 20h /
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)
olivier.girard 1286d 20h /
120 update tools changelog... olivier.girard 1318d 03h /
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 1318d 04h /
118 Changelog update (move to modified BSD license). olivier.girard 1318d 21h /
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 1318d 21h /
116 Update documentation to reflect the latest core updates. olivier.girard 1334d 21h /
115 Add linker script example. olivier.girard 1343d 20h /
114 Improved the VerifyCPU_ID procedure. olivier.girard 1346d 20h /
113 Created ChangeLog files... olivier.girard 1347d 20h /
112 Modified comment. olivier.girard 1351d 19h /
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1352d 20h /
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.
olivier.girard 1353d 20h /
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 1407d 04h /
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 1408d 17h /
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 1408d 17h /
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1408d 18h /
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1423d 19h /

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