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Rev Log message Author Age Path
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 1224d 15h /
133 Add support for new CPU version. olivier.girard 1224d 15h /
132 Update FPGA examples with the POP.B bug fix olivier.girard 1237d 15h /
131 Update ChangeLog olivier.girard 1245d 14h /
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 1245d 14h /
129 Update ChangeLog olivier.girard 1321d 15h /
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 1321d 15h /
127 update changelog... olivier.girard 1357d 14h /
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.
olivier.girard 1357d 14h /
125 update changelog... olivier.girard 1371d 17h /
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.
olivier.girard 1372d 04h /
123 update changelog... olivier.girard 1393d 15h /
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 1393d 15h /
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)
olivier.girard 1465d 16h /
120 update tools changelog... olivier.girard 1496d 22h /
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 1496d 23h /
118 Changelog update (move to modified BSD license). olivier.girard 1497d 16h /
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 1497d 16h /
116 Update documentation to reflect the latest core updates. olivier.girard 1513d 17h /
115 Add linker script example. olivier.girard 1522d 16h /
114 Improved the VerifyCPU_ID procedure. olivier.girard 1525d 15h /
113 Created ChangeLog files... olivier.girard 1526d 16h /
112 Modified comment. olivier.girard 1530d 15h /
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 1531d 15h /
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.
olivier.girard 1532d 15h /
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 1586d 00h /
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 1587d 13h /
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 1587d 13h /
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 1587d 14h /
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 1602d 15h /

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