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Rev Log message Author Age Path
16 Removed useless code kingmu 2145d 11h /
15 Replaced with more advanced version created by Thiagarajan kingmu 2148d 13h /
14 Removed Xilinx warning caused by missing signals in sensitivity list kingmu 2148d 13h /
13 Merged rewrite of singleDouble into trunk kingmu 2149d 11h /
12 Trivial updates kingmu 2155d 18h /
11 This is a perl model which functionally simulates manchester encoding and decoding. thiagu_comp 2157d 03h /
10 This folder contains the perl model, which functionally simulates manchester encoding and decoding. This can be used to validate the HDL model. thiagu_comp 2157d 04h /
9 Modified next state logic to avoid gated clock on net clock_zero_en_0000 during bitgen process. As a default case the counter enables are de-asserted. thiagu_comp 2160d 04h /
8 Removed old singleDouble and added .ucf kingmu 2163d 06h /
7 Added new singleDouble files kingmu 2163d 07h /
6 Branching trunk to experiment with new singleDouble module kingmu 2163d 07h /
5 Tagging 1.0 release kingmu 2163d 16h /
4 Updated simulation files to reflect new module names kingmu 2168d 11h /
3 Renamed files/modules. Added documentation. kingmu 2168d 12h /
2 initial commit kingmu 2169d 12h /
1 The project was created and the structure was created root 2176d 04h /

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