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Rev Log message Author Age Path
16 Removed useless code kingmu 1747d 15h /
15 Replaced with more advanced version created by Thiagarajan kingmu 1750d 17h /
14 Removed Xilinx warning caused by missing signals in sensitivity list kingmu 1750d 17h /
13 Merged rewrite of singleDouble into trunk kingmu 1751d 15h /
12 Trivial updates kingmu 1757d 21h /
11 This is a perl model which functionally simulates manchester encoding and decoding. thiagu_comp 1759d 07h /
10 This folder contains the perl model, which functionally simulates manchester encoding and decoding. This can be used to validate the HDL model. thiagu_comp 1759d 07h /
9 Modified next state logic to avoid gated clock on net clock_zero_en_0000 during bitgen process. As a default case the counter enables are de-asserted. thiagu_comp 1762d 08h /
8 Removed old singleDouble and added .ucf kingmu 1765d 10h /
7 Added new singleDouble files kingmu 1765d 11h /
6 Branching trunk to experiment with new singleDouble module kingmu 1765d 11h /
5 Tagging 1.0 release kingmu 1765d 20h /
4 Updated simulation files to reflect new module names kingmu 1770d 15h /
3 Renamed files/modules. Added documentation. kingmu 1770d 16h /
2 initial commit kingmu 1771d 16h /
1 The project was created and the structure was created root 1778d 07h /

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