OpenCores

Subversion Repositories manchesterwireless

[/] - Rev 16

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
16 Removed useless code kingmu 1841d 19h /
15 Replaced with more advanced version created by Thiagarajan kingmu 1844d 21h /
14 Removed Xilinx warning caused by missing signals in sensitivity list kingmu 1844d 21h /
13 Merged rewrite of singleDouble into trunk kingmu 1845d 19h /
12 Trivial updates kingmu 1852d 01h /
11 This is a perl model which functionally simulates manchester encoding and decoding. thiagu_comp 1853d 11h /
10 This folder contains the perl model, which functionally simulates manchester encoding and decoding. This can be used to validate the HDL model. thiagu_comp 1853d 11h /
9 Modified next state logic to avoid gated clock on net clock_zero_en_0000 during bitgen process. As a default case the counter enables are de-asserted. thiagu_comp 1856d 12h /
8 Removed old singleDouble and added .ucf kingmu 1859d 14h /
7 Added new singleDouble files kingmu 1859d 14h /
6 Branching trunk to experiment with new singleDouble module kingmu 1859d 15h /
5 Tagging 1.0 release kingmu 1860d 00h /
4 Updated simulation files to reflect new module names kingmu 1864d 19h /
3 Renamed files/modules. Added documentation. kingmu 1864d 19h /
2 initial commit kingmu 1865d 20h /
1 The project was created and the structure was created root 1872d 11h /

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.