Subversion Repositories manchesterwireless

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Rev Log message Author Age Path
16 Removed useless code kingmu 2406d 02h /
15 Replaced with more advanced version created by Thiagarajan kingmu 2409d 04h /
14 Removed Xilinx warning caused by missing signals in sensitivity list kingmu 2409d 04h /
13 Merged rewrite of singleDouble into trunk kingmu 2410d 02h /
12 Trivial updates kingmu 2416d 08h /
11 This is a perl model which functionally simulates manchester encoding and decoding. thiagu_comp 2417d 18h /
10 This folder contains the perl model, which functionally simulates manchester encoding and decoding. This can be used to validate the HDL model. thiagu_comp 2417d 18h /
9 Modified next state logic to avoid gated clock on net clock_zero_en_0000 during bitgen process. As a default case the counter enables are de-asserted. thiagu_comp 2420d 19h /
8 Removed old singleDouble and added .ucf kingmu 2423d 21h /
7 Added new singleDouble files kingmu 2423d 21h /
6 Branching trunk to experiment with new singleDouble module kingmu 2423d 22h /
5 Tagging 1.0 release kingmu 2424d 07h /
4 Updated simulation files to reflect new module names kingmu 2429d 02h /
3 Renamed files/modules. Added documentation. kingmu 2429d 03h /
2 initial commit kingmu 2430d 03h /
1 The project was created and the structure was created root 2436d 18h /

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