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29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 905d 00h /
28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 905d 07h /
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 905d 07h /
26 Updated test case. edn_walter 907d 02h /
25 Updated SOPC Builder component and example system. edn_walter 908d 01h /
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 908d 02h /
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 908d 20h /
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 909d 00h /
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 909d 21h /
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 914d 01h /
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 914d 01h /
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 914d 01h /
17 Updated reg.v content. edn_walter 914d 19h /
16 Try to add sth. edn_walter 918d 12h /
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 920d 20h /
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 922d 20h /
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 923d 20h /
12 Added parser support for vlan tagged frames. edn_walter 924d 19h /
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 925d 20h /
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 926d 20h /
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 927d 20h /
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 928d 02h /
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 928d 03h /
6 Reduced the size of the Vendor specific simulation library file. ash_riple 930d 03h /
5 Added dcfifo to store ptp time stamps. ash_riple 930d 19h /
4 Added source code and unit test for TSU. ash_riple 931d 19h /
3 Added function block RTC and its unit test. ash_riple 938d 19h /
2 Try to add sth. to the repository. ash_riple 938d 19h /
1 The project and the structure was created root 939d 02h /

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