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29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 872d 02h /
28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 872d 08h /
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 872d 08h /
26 Updated test case. edn_walter 874d 03h /
25 Updated SOPC Builder component and example system. edn_walter 875d 02h /
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 875d 04h /
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 875d 22h /
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 876d 02h /
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 876d 22h /
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 881d 03h /
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 881d 03h /
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 881d 03h /
17 Updated reg.v content. edn_walter 881d 21h /
16 Try to add sth. edn_walter 885d 13h /
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 887d 22h /
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 889d 22h /
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 890d 22h /
12 Added parser support for vlan tagged frames. edn_walter 891d 20h /
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 892d 22h /
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 893d 22h /
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 894d 22h /
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 895d 04h /
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 895d 05h /
6 Reduced the size of the Vendor specific simulation library file. ash_riple 897d 05h /
5 Added dcfifo to store ptp time stamps. ash_riple 897d 20h /
4 Added source code and unit test for TSU. ash_riple 898d 21h /
3 Added function block RTC and its unit test. ash_riple 905d 21h /
2 Try to add sth. to the repository. ash_riple 905d 21h /
1 The project and the structure was created root 906d 04h /

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