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29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 925d 04h /
28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 925d 10h /
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 925d 10h /
26 Updated test case. edn_walter 927d 05h /
25 Updated SOPC Builder component and example system. edn_walter 928d 04h /
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 928d 05h /
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 928d 23h /
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 929d 03h /
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 930d 00h /
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 934d 04h /
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 934d 04h /
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 934d 04h /
17 Updated reg.v content. edn_walter 934d 22h /
16 Try to add sth. edn_walter 938d 15h /
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 940d 23h /
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 942d 23h /
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 944d 00h /
12 Added parser support for vlan tagged frames. edn_walter 944d 22h /
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 945d 23h /
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 947d 00h /

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