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29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 875d 01h /
28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 875d 07h /
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 875d 08h /
26 Updated test case. edn_walter 877d 03h /
25 Updated SOPC Builder component and example system. edn_walter 878d 01h /
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 878d 03h /
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 878d 21h /
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 879d 01h /
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 879d 22h /
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 884d 02h /
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 884d 02h /
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 884d 02h /
17 Updated reg.v content. edn_walter 884d 20h /
16 Try to add sth. edn_walter 888d 12h /
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 890d 21h /
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 892d 21h /
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 893d 21h /
12 Added parser support for vlan tagged frames. edn_walter 894d 20h /
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 895d 21h /
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 896d 21h /

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