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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 1385d 14h /
359 Verilator linting fixes olof 1387d 16h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 1389d 06h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 1389d 06h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1389d 08h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 1389d 09h /
354 Whitespace cleanup olof 1389d 09h /
353 Inherit fixes for bit width of constants from ORPSoC olof 1391d 10h /
352 Removed delayed assignments from rtl code olof 1395d 16h /
351 Turn defines into parameters in eth_cop olof 1404d 06h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1404d 07h /
349 Make all parameters configurable from top level olof 1405d 07h /
348 Added option to dump VCD files olof 1406d 06h /
347 Added information about running with Icarus Verilog olof 1406d 07h /
346 Updated project location olof 1406d 09h /
345 Temporarily disable failing tests olof 1406d 11h /
344 bit 9 in phy control register is self clearing olof 1412d 13h /
343 Address miss should not be asserted on short frames olof 1416d 09h /
342 Added cast to avoid inequality when comparing different data types olof 1416d 09h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 1416d 09h /

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