Subversion Repositories ethmac

[/] - Rev 360


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 1174d 10h /
359 Verilator linting fixes olof 1176d 12h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 1178d 02h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 1178d 02h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1178d 04h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 1178d 05h /
354 Whitespace cleanup olof 1178d 05h /
353 Inherit fixes for bit width of constants from ORPSoC olof 1180d 07h /
352 Removed delayed assignments from rtl code olof 1184d 13h /
351 Turn defines into parameters in eth_cop olof 1193d 02h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1193d 03h /
349 Make all parameters configurable from top level olof 1194d 04h /
348 Added option to dump VCD files olof 1195d 03h /
347 Added information about running with Icarus Verilog olof 1195d 03h /
346 Updated project location olof 1195d 05h /
345 Temporarily disable failing tests olof 1195d 07h /
344 bit 9 in phy control register is self clearing olof 1201d 09h /
343 Address miss should not be asserted on short frames olof 1205d 05h /
342 Added cast to avoid inequality when comparing different data types olof 1205d 05h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 1205d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2014, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.