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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 1304d 02h /
359 Verilator linting fixes olof 1306d 04h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 1307d 18h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 1307d 18h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1307d 20h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 1307d 21h /
354 Whitespace cleanup olof 1307d 21h /
353 Inherit fixes for bit width of constants from ORPSoC olof 1309d 22h /
352 Removed delayed assignments from rtl code olof 1314d 04h /
351 Turn defines into parameters in eth_cop olof 1322d 18h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1322d 19h /
349 Make all parameters configurable from top level olof 1323d 19h /
348 Added option to dump VCD files olof 1324d 18h /
347 Added information about running with Icarus Verilog olof 1324d 19h /
346 Updated project location olof 1324d 21h /
345 Temporarily disable failing tests olof 1324d 23h /
344 bit 9 in phy control register is self clearing olof 1331d 01h /
343 Address miss should not be asserted on short frames olof 1334d 21h /
342 Added cast to avoid inequality when comparing different data types olof 1334d 21h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 1334d 21h /

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