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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 1263d 19h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 1326d 16h /
366 Readded eth_top.v with a deprecation warning olof 1450d 20h /
365 Whitespace cleanup olof 1451d 19h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 1452d 17h /
363 quartus project files unneback 1453d 01h /
362 added Makefiles to build project unneback 1453d 01h /
361 created branch unneback unneback 1453d 02h /
360 Added partial implementation of the debug register from ORPSoC olof 1454d 00h /
359 Verilator linting fixes olof 1456d 02h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 1457d 16h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 1457d 17h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1457d 18h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 1457d 19h /
354 Whitespace cleanup olof 1457d 20h /
353 Inherit fixes for bit width of constants from ORPSoC olof 1459d 21h /
352 Removed delayed assignments from rtl code olof 1464d 03h /
351 Turn defines into parameters in eth_cop olof 1472d 17h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1472d 17h /
349 Make all parameters configurable from top level olof 1473d 18h /

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