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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 360

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360 Added partial implementation of the debug register from ORPSoC olof 1453d 22h /ethmac/trunk/rtl/verilog/ethmac_defines.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1457d 16h /ethmac/trunk/rtl/verilog/ethmac_defines.v
351 Turn defines into parameters in eth_cop olof 1472d 15h /ethmac/trunk/rtl/verilog/eth_defines.v
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1472d 15h /ethmac/trunk/rtl/verilog/eth_defines.v
346 Updated project location olof 1474d 18h /ethmac/trunk/rtl/verilog/eth_defines.v
338 root 2278d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
335 New directory structure. root 2336d 01h /ethmac/trunk/rtl/verilog/eth_defines.v
330 Warning fixes. igorm 3812d 22h /ethmac/trunk/rtl/verilog/eth_defines.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 4279d 17h /ethmac/trunk/rtl/verilog/eth_defines.v
302 mbist signals updated according to newest convention markom 4306d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
297 Artisan ram instance added. simons 4369d 19h /ethmac/trunk/rtl/verilog/eth_defines.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 4431d 23h /ethmac/trunk/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 4637d 17h /ethmac/trunk/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 4641d 21h /ethmac/trunk/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 4655d 17h /ethmac/trunk/rtl/verilog/eth_defines.v
232 fpga define added. mohor 4663d 16h /ethmac/trunk/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 4677d 18h /ethmac/trunk/rtl/verilog/eth_defines.v
211 Bist added. mohor 4677d 19h /ethmac/trunk/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 4694d 17h /ethmac/trunk/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 4713d 17h /ethmac/trunk/rtl/verilog/eth_defines.v

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