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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 360

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360 Added partial implementation of the debug register from ORPSoC olof 649d 09h /ethmac/trunk/rtl/verilog/ethmac_defines.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 653d 03h /ethmac/trunk/rtl/verilog/ethmac_defines.v
351 Turn defines into parameters in eth_cop olof 668d 01h /ethmac/trunk/rtl/verilog/eth_defines.v
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 668d 02h /ethmac/trunk/rtl/verilog/eth_defines.v
346 Updated project location olof 670d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
338 root 1474d 07h /ethmac/trunk/rtl/verilog/eth_defines.v
335 New directory structure. root 1531d 12h /ethmac/trunk/rtl/verilog/eth_defines.v
330 Warning fixes. igorm 3008d 09h /ethmac/trunk/rtl/verilog/eth_defines.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 3475d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
302 mbist signals updated according to newest convention markom 3501d 14h /ethmac/trunk/rtl/verilog/eth_defines.v
297 Artisan ram instance added. simons 3565d 05h /ethmac/trunk/rtl/verilog/eth_defines.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 3627d 10h /ethmac/trunk/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 3833d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 3837d 08h /ethmac/trunk/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 3851d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
232 fpga define added. mohor 3859d 03h /ethmac/trunk/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 3873d 05h /ethmac/trunk/rtl/verilog/eth_defines.v
211 Bist added. mohor 3873d 05h /ethmac/trunk/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 3890d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 3909d 03h /ethmac/trunk/rtl/verilog/eth_defines.v

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