OpenCores

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Rev 353

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
353 Inherit fixes for bit width of constants from ORPSoC olof 1355d 03h /ethmac/trunk/rtl/verilog/eth_txethmac.v
352 Removed delayed assignments from rtl code olof 1359d 08h /ethmac/trunk/rtl/verilog/eth_txethmac.v
349 Make all parameters configurable from top level olof 1369d 00h /ethmac/trunk/rtl/verilog/eth_txethmac.v
346 Updated project location olof 1370d 01h /ethmac/trunk/rtl/verilog/eth_txethmac.v
338 root 2174d 04h /ethmac/trunk/rtl/verilog/eth_txethmac.v
335 New directory structure. root 2231d 09h /ethmac/trunk/rtl/verilog/eth_txethmac.v
328 Delayed CRC fixed. igorm 3708d 07h /ethmac/trunk/rtl/verilog/eth_txethmac.v
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 4461d 05h /ethmac/trunk/rtl/verilog/eth_txethmac.v
79 RetryCntLatched was unused and removed from design mohor 4799d 02h /ethmac/trunk/rtl/verilog/eth_txethmac.v
72 Retry is not activated when a Tx Underrun occured mohor 4803d 06h /ethmac/trunk/rtl/verilog/eth_txethmac.v
43 Tx status is written back to the BD. mohor 4814d 10h /ethmac/trunk/rtl/verilog/eth_txethmac.v
37 Link in the header changed. mohor 4833d 08h /ethmac/trunk/rtl/verilog/eth_txethmac.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 4929d 10h /ethmac/trunk/rtl/verilog/eth_txethmac.v
18 Few little NCSIM warnings fixed. mohor 4967d 05h /ethmac/trunk/rtl/verilog/eth_txethmac.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 5003d 04h /ethmac/trunk/rtl/verilog/eth_txethmac.v

powered by: WebSVN 2.1.0

© copyright 1999-2015 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.