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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Rev 353

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Rev Log message Author Age Path
353 Inherit fixes for bit width of constants from ORPSoC olof 1145d 05h /ethmac/trunk/rtl/verilog/eth_txethmac.v
352 Removed delayed assignments from rtl code olof 1149d 11h /ethmac/trunk/rtl/verilog/eth_txethmac.v
349 Make all parameters configurable from top level olof 1159d 02h /ethmac/trunk/rtl/verilog/eth_txethmac.v
346 Updated project location olof 1160d 04h /ethmac/trunk/rtl/verilog/eth_txethmac.v
338 root 1964d 06h /ethmac/trunk/rtl/verilog/eth_txethmac.v
335 New directory structure. root 2021d 12h /ethmac/trunk/rtl/verilog/eth_txethmac.v
328 Delayed CRC fixed. igorm 3498d 10h /ethmac/trunk/rtl/verilog/eth_txethmac.v
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 4251d 08h /ethmac/trunk/rtl/verilog/eth_txethmac.v
79 RetryCntLatched was unused and removed from design mohor 4589d 05h /ethmac/trunk/rtl/verilog/eth_txethmac.v
72 Retry is not activated when a Tx Underrun occured mohor 4593d 09h /ethmac/trunk/rtl/verilog/eth_txethmac.v
43 Tx status is written back to the BD. mohor 4604d 12h /ethmac/trunk/rtl/verilog/eth_txethmac.v
37 Link in the header changed. mohor 4623d 11h /ethmac/trunk/rtl/verilog/eth_txethmac.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 4719d 13h /ethmac/trunk/rtl/verilog/eth_txethmac.v
18 Few little NCSIM warnings fixed. mohor 4757d 07h /ethmac/trunk/rtl/verilog/eth_txethmac.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 4793d 07h /ethmac/trunk/rtl/verilog/eth_txethmac.v

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