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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 356

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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1205d 06h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
354 Whitespace cleanup olof 1205d 07h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
352 Removed delayed assignments from rtl code olof 1211d 15h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 1222d 08h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
338 root 2026d 10h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 2083d 15h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 3560d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 4004d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 4005d 10h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 4027d 07h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 4053d 17h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 4117d 08h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 4417d 08h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 4425d 09h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 4442d 07h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 4504d 09h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v

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