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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 1399d 05h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 1409d 22h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
338 root 2214d 00h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 2271d 05h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 3748d 03h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 4192d 03h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 4193d 01h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 4214d 21h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 4241d 08h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 4304d 23h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 4604d 22h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 4612d 23h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 4629d 21h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 4691d 23h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v

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