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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 1181d 15h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
349 Make all parameters configurable from top level olof 1191d 06h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 1202d 07h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
338 root 1996d 10h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
335 New directory structure. root 2053d 15h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
330 Warning fixes. igorm 3530d 12h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 3831d 10h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 3871d 16h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 4352d 23h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 4355d 08h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
65 Testbench fixed, code simplified, unused signals removed. mohor 4631d 18h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
62 RxAbort is an output. No need to have is declared as wire. mohor 4632d 11h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
58 File format changed. mohor 4632d 14h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
53 Addition of new module eth_addrcheck.v billditt 4633d 04h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
37 Link in the header changed. mohor 4655d 15h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 4751d 16h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
18 Few little NCSIM warnings fixed. mohor 4789d 11h /ethmac/trunk/rtl/verilog/eth_rxethmac.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 4825d 10h /ethmac/trunk/rtl/verilog/eth_rxethmac.v

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