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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_register.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 1237d 19h /ethmac/trunk/rtl/verilog/eth_register.v
346 Updated project location olof 1248d 11h /ethmac/trunk/rtl/verilog/eth_register.v
338 root 2052d 14h /ethmac/trunk/rtl/verilog/eth_register.v
335 New directory structure. root 2109d 19h /ethmac/trunk/rtl/verilog/eth_register.v
138 Synchronous reset added. mohor 4506d 07h /ethmac/trunk/rtl/verilog/eth_register.v
136 Parameter ResetValue changed to capital letters. mohor 4506d 17h /ethmac/trunk/rtl/verilog/eth_register.v
74 Reset values are passed to registers through parameters mohor 4677d 13h /ethmac/trunk/rtl/verilog/eth_register.v
37 Link in the header changed. mohor 4711d 19h /ethmac/trunk/rtl/verilog/eth_register.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 4807d 20h /ethmac/trunk/rtl/verilog/eth_register.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 4881d 14h /ethmac/trunk/rtl/verilog/eth_register.v

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