OpenCores

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Rev 352

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 1091d 11h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
346 Updated project location olof 1102d 04h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
338 root 1906d 06h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
335 New directory structure. root 1963d 11h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
272 When control packets were received, they were ignored in some cases. tadejm 4201d 07h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 4262d 19h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
37 Link in the header changed. mohor 4565d 11h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 4661d 12h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 4735d 06h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.