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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 1242d 16h /ethmac/trunk/rtl/verilog/eth_fifo.v
346 Updated project location olof 1253d 09h /ethmac/trunk/rtl/verilog/eth_fifo.v
338 root 2057d 11h /ethmac/trunk/rtl/verilog/eth_fifo.v
335 New directory structure. root 2114d 16h /ethmac/trunk/rtl/verilog/eth_fifo.v
330 Warning fixes. igorm 3591d 14h /ethmac/trunk/rtl/verilog/eth_fifo.v
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 4627d 13h /ethmac/trunk/rtl/verilog/eth_fifo.v
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 4655d 13h /ethmac/trunk/rtl/verilog/eth_fifo.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 4703d 10h /ethmac/trunk/rtl/verilog/eth_fifo.v

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