OpenCores

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Rev 365

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
365 Whitespace cleanup olof 987d 11h /ethmac/trunk/rtl/verilog/eth_fifo.v
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 993d 08h /ethmac/trunk/rtl/verilog/eth_fifo.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 993d 10h /ethmac/trunk/rtl/verilog/eth_fifo.v
354 Whitespace cleanup olof 993d 11h /ethmac/trunk/rtl/verilog/eth_fifo.v
352 Removed delayed assignments from rtl code olof 999d 19h /ethmac/trunk/rtl/verilog/eth_fifo.v
346 Updated project location olof 1010d 11h /ethmac/trunk/rtl/verilog/eth_fifo.v
338 root 1814d 14h /ethmac/trunk/rtl/verilog/eth_fifo.v
335 New directory structure. root 1871d 19h /ethmac/trunk/rtl/verilog/eth_fifo.v
330 Warning fixes. igorm 3348d 16h /ethmac/trunk/rtl/verilog/eth_fifo.v
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 4384d 15h /ethmac/trunk/rtl/verilog/eth_fifo.v
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 4412d 15h /ethmac/trunk/rtl/verilog/eth_fifo.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 4460d 12h /ethmac/trunk/rtl/verilog/eth_fifo.v

powered by: WebSVN 2.1.0

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.