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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 342

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342 Added cast to avoid inequality when comparing different data types olof 1673d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 2467d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 2525d 03h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 3973d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 4002d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 4333d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 4446d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 4495d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 4553d 01h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 4753d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 4754d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 4762d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 4818d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 4823d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 4824d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 4824d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 4826d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 4826d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 4832d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 4858d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 4858d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 4868d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 4886d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 4888d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 4890d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 4890d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 4893d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 4893d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 4893d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 4893d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v

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