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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 342

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342 Added cast to avoid inequality when comparing different data types olof 1677d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 2471d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 2529d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 3977d 02h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 4005d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 4337d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 4449d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 4499d 02h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 4556d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 4757d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 4758d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 4766d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 4822d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 4827d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 4828d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 4828d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 4830d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 4830d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 4835d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 4862d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v

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