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Rev Log message Author Age Path
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 4713d 03h /ethmac/trunk/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 4713d 04h /ethmac/trunk/
30 BD section updated. mohor 4715d 01h /ethmac/trunk/
29 Generic memory model is used. Defines are changed for the same reason. mohor 4734d 23h /ethmac/trunk/
28 New release. Name changed to lower case. mohor 4737d 15h /ethmac/trunk/
27 File names changed to lower case. mohor 4737d 15h /ethmac/trunk/
26 First release of product brief. mohor 4737d 15h /ethmac/trunk/
25 First release of product brief. mohor 4737d 15h /ethmac/trunk/
24 Log file added. mohor 4760d 02h /ethmac/trunk/
23 Number of addresses (wb_adr_i) minimized. mohor 4760d 02h /ethmac/trunk/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 4760d 05h /ethmac/trunk/
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 4761d 02h /ethmac/trunk/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 4784d 23h /ethmac/trunk/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 4784d 23h /ethmac/trunk/
18 Few little NCSIM warnings fixed. mohor 4798d 00h /ethmac/trunk/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 4825d 00h /ethmac/trunk/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 4832d 05h /ethmac/trunk/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 4833d 23h /ethmac/trunk/
14 Unconnected signals are now connected. mohor 4838d 04h /ethmac/trunk/
13 New directory structure. Files upodated and put together. mohor 4840d 13h /ethmac/trunk/

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