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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 1038d 20h /ethmac/trunk/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 1101d 17h /ethmac/trunk/
366 Readded eth_top.v with a deprecation warning olof 1225d 21h /ethmac/trunk/
365 Whitespace cleanup olof 1226d 20h /ethmac/trunk/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 1227d 18h /ethmac/trunk/
360 Added partial implementation of the debug register from ORPSoC olof 1229d 01h /ethmac/trunk/
359 Verilator linting fixes olof 1231d 04h /ethmac/trunk/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 1232d 18h /ethmac/trunk/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 1232d 18h /ethmac/trunk/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 1232d 20h /ethmac/trunk/
355 Import Julius Baxter's verilator hints from ORPSoC olof 1232d 20h /ethmac/trunk/
354 Whitespace cleanup olof 1232d 21h /ethmac/trunk/
353 Inherit fixes for bit width of constants from ORPSoC olof 1234d 22h /ethmac/trunk/
352 Removed delayed assignments from rtl code olof 1239d 04h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 1247d 18h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 1247d 19h /ethmac/trunk/
349 Make all parameters configurable from top level olof 1248d 19h /ethmac/trunk/
348 Added option to dump VCD files olof 1249d 18h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 1249d 19h /ethmac/trunk/
346 Updated project location olof 1249d 21h /ethmac/trunk/

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