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Rev Log message Author Age Path
338 root 1959d 22h /ethmac/tags/rel_6/
335 New directory structure. root 2017d 03h /ethmac/tags/rel_6/
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 4354d 21h /ethmac/tags/rel_6/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 4354d 21h /ethmac/tags/rel_6/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 4357d 21h /ethmac/tags/rel_6/
218 Typo error fixed. (When using Bist) mohor 4357d 23h /ethmac/tags/rel_6/
217 Bist supported. mohor 4357d 23h /ethmac/tags/rel_6/
216 Bist signals added. mohor 4357d 23h /ethmac/tags/rel_6/
215 Bist supported. mohor 4358d 00h /ethmac/tags/rel_6/
214 Signals for WISHBONE B3 compliant interface added. mohor 4358d 20h /ethmac/tags/rel_6/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 4358d 20h /ethmac/tags/rel_6/
212 Minor $display change. mohor 4358d 20h /ethmac/tags/rel_6/
211 Bist added. mohor 4358d 20h /ethmac/tags/rel_6/
210 BIST added. mohor 4358d 20h /ethmac/tags/rel_6/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 4360d 00h /ethmac/tags/rel_6/
208 Virtual Silicon RAMs moved to lib directory tadej 4375d 18h /ethmac/tags/rel_6/
207 Virtual Silicon RAM support fixed tadej 4375d 18h /ethmac/tags/rel_6/
206 Virtual Silicon RAM added to the simulation. mohor 4375d 18h /ethmac/tags/rel_6/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 4375d 18h /ethmac/tags/rel_6/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 4375d 19h /ethmac/tags/rel_6/

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