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338 root 1935d 14h /ethmac/tags/rel_5/
335 New directory structure. root 1992d 19h /ethmac/tags/rel_5/
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 4333d 13h /ethmac/tags/rel_5/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 4333d 13h /ethmac/tags/rel_5/
218 Typo error fixed. (When using Bist) mohor 4333d 15h /ethmac/tags/rel_5/
217 Bist supported. mohor 4333d 15h /ethmac/tags/rel_5/
216 Bist signals added. mohor 4333d 16h /ethmac/tags/rel_5/
215 Bist supported. mohor 4333d 16h /ethmac/tags/rel_5/
214 Signals for WISHBONE B3 compliant interface added. mohor 4334d 12h /ethmac/tags/rel_5/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 4334d 12h /ethmac/tags/rel_5/
212 Minor $display change. mohor 4334d 12h /ethmac/tags/rel_5/
211 Bist added. mohor 4334d 13h /ethmac/tags/rel_5/
210 BIST added. mohor 4334d 13h /ethmac/tags/rel_5/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 4335d 16h /ethmac/tags/rel_5/
208 Virtual Silicon RAMs moved to lib directory tadej 4351d 10h /ethmac/tags/rel_5/
207 Virtual Silicon RAM support fixed tadej 4351d 10h /ethmac/tags/rel_5/
206 Virtual Silicon RAM added to the simulation. mohor 4351d 10h /ethmac/tags/rel_5/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 4351d 11h /ethmac/tags/rel_5/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 4351d 11h /ethmac/tags/rel_5/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 4351d 11h /ethmac/tags/rel_5/

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