Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_3/] - Rev 367


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 2474d 02h /ethmac/tags/rel_3/
335 New directory structure. root 2531d 08h /ethmac/tags/rel_3/
142 This commit was manufactured by cvs2svn to create tag 'rel_3'. 4927d 19h /ethmac/tags/rel_3/
141 Syntax error fixed. mohor 4927d 19h /ethmac/tags/rel_3/
140 Syntax error fixed. mohor 4927d 19h /ethmac/tags/rel_3/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 4927d 19h /ethmac/tags/rel_3/
138 Synchronous reset added. mohor 4927d 19h /ethmac/tags/rel_3/
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 4927d 19h /ethmac/tags/rel_3/
136 Parameter ResetValue changed to capital letters. mohor 4928d 05h /ethmac/tags/rel_3/
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 4929d 21h /ethmac/tags/rel_3/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 4929d 22h /ethmac/tags/rel_3/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 4929d 23h /ethmac/tags/rel_3/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 4929d 23h /ethmac/tags/rel_3/
131 LinkFail signal was not latching appropriate bit. mohor 4929d 23h /ethmac/tags/rel_3/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 4930d 00h /ethmac/tags/rel_3/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 4930d 00h /ethmac/tags/rel_3/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 4949d 23h /ethmac/tags/rel_3/
126 InvalidSymbol generation changed. mohor 4949d 23h /ethmac/tags/rel_3/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 4949d 23h /ethmac/tags/rel_3/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 4950d 00h /ethmac/tags/rel_3/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2016, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.