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Rev Log message Author Age Path
245 Rev 1.7. mohor 3838d 16h /ethmac/tags/rel_17/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 3838d 18h /ethmac/tags/rel_17/
243 Late collision is not reported any more. tadejm 3838d 23h /ethmac/tags/rel_17/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 3839d 14h /ethmac/tags/rel_17/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 3839d 14h /ethmac/tags/rel_17/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 3839d 14h /ethmac/tags/rel_17/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 3839d 14h /ethmac/tags/rel_17/
238 Defines fixed to use generic RAM by default. mohor 3851d 18h /ethmac/tags/rel_17/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 3854d 00h /ethmac/tags/rel_17/
235 rev 4. mohor 3854d 14h /ethmac/tags/rel_17/
234 Figure list assed to the revision 3. mohor 3854d 23h /ethmac/tags/rel_17/
233 Revision 0.3 released. Some figures added. mohor 3854d 23h /ethmac/tags/rel_17/
232 fpga define added. mohor 3859d 18h /ethmac/tags/rel_17/
231 Description of Core Modules added (figure). mohor 3861d 19h /ethmac/tags/rel_17/
229 case changed to casex. mohor 3865d 16h /ethmac/tags/rel_17/
227 Changed BIST scan signals. tadejm 3865d 20h /ethmac/tags/rel_17/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 3865d 21h /ethmac/tags/rel_17/
225 Some minor changes. tadejm 3865d 21h /ethmac/tags/rel_17/
224 Signals for a wave window in Modelsim. tadejm 3865d 22h /ethmac/tags/rel_17/
223 Some code changed due to bug fixes. tadejm 3865d 23h /ethmac/tags/rel_17/

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