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Rev Log message Author Age Path
338 root 2005d 22h /ethmac/tags/rel_14/rtl/
335 New directory structure. root 2063d 04h /ethmac/tags/rel_14/rtl/
271 This commit was manufactured by cvs2svn to create tag 'rel_14'. 4302d 01h /ethmac/tags/rel_14/rtl/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 4302d 01h /ethmac/tags/rel_14/rtl/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 4303d 01h /ethmac/tags/rel_14/rtl/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 4362d 00h /ethmac/tags/rel_14/rtl/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 4362d 12h /ethmac/tags/rel_14/rtl/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 4363d 13h /ethmac/tags/rel_14/rtl/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 4363d 13h /ethmac/tags/rel_14/rtl/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 4363d 13h /ethmac/tags/rel_14/rtl/
255 TPauseRq synchronized to tx_clk. mohor 4363d 13h /ethmac/tags/rel_14/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 4364d 19h /ethmac/tags/rel_14/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 4364d 20h /ethmac/tags/rel_14/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 4364d 20h /ethmac/tags/rel_14/rtl/
248 wb_rst_i is used for MIIM reset. mohor 4365d 20h /ethmac/tags/rel_14/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 4368d 23h /ethmac/tags/rel_14/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 4369d 19h /ethmac/tags/rel_14/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 4370d 15h /ethmac/tags/rel_14/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 4370d 15h /ethmac/tags/rel_14/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 4370d 15h /ethmac/tags/rel_14/rtl/

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